NAND Flash Cache Programming for TLC Data Integrity
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Solution Overview
Problem
In high-speed storage systems, the data-in time in page buffers of NAND flash memory limits overall system performance due to prolonged programming and verification times, especially in multi-level cell modes where each memory cell stores multiple bits, necessitating optimization of cache programming to reduce data-in time without losing original programming data.
Innovation Solution
The method involves programming and verifying memory cells in stages, discarding confirmed logic pages from data latches and uploading new data to cache latches, using inhibit information to control programming, and employing read reference voltages to verify states and recover data in case of failures, optimizing cache usage in page buffers for NAND flash memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If programming and verification are performed for all logic states before discarding data, then data integrity is ensured, but programming time and data-in time are prolonged
Solution Approach 1:
The patent applies preliminary action by discarding the first logic page from data latches before completing verification of all logic states. The system discards data preliminarily based on partial verification (first group of logic states), and only recovers data if programming failure is detected later. This resolves the contradiction by reducing data-in time through early data disposal while maintaining data integrity through the recovery mechanism.
Solution Approach 2:
The patent implements the discarding and recovering principle by allowing data to be discarded from data latches after partial programming verification, with a recovery mechanism in place. If programming failure occurs, the original data can be recovered from the memory cells. This enables early data disposal to reduce data-in time while ensuring data integrity through the recoverable design.
2Productivity
If data is discarded early to reduce data-in time, then programming speed improves, but risk of data loss increases
Solution Approach 1:
The system performs preliminary discarding of data from latches before complete programming verification, enabling faster programming speed. The risk of data loss is mitigated by the recovery mechanism that can restore original data from memory cells if programming failure is detected, thus maintaining data safety despite early data disposal.
Solution Approach 2:
The patent applies discarding and recovering by allowing early data disposal to improve programming speed while implementing a recovery mechanism. If programming fails, the original data stored in memory cells can be recovered, ensuring data safety is maintained even though data is discarded early in the process.
3Reliability
If all programming data are kept in page buffers throughout the operation, then data recovery is ensured, but cache programming efficiency is reduced
Solution Approach 1:
The patent implements discarding and recovering by allowing data to be discarded from page buffer data latches after partial verification, improving cache programming efficiency. The reliability of data recovery is maintained through the mechanism that can restore original data from memory cells if programming failure occurs, thus resolving the contradiction between efficiency and recovery capability.
Solution Approach 2:
The system applies taking out by extracting (discarding) data from the page buffer data latches after partial programming verification. This removes unnecessary data retention requirements, improving cache programming efficiency. The data recovery capability is preserved through the ability to retrieve original data from memory cells if needed.
4Manufacturing precision
If multiple logic pages are programmed sequentially with full verification, then programming accuracy is maintained, but overall programming time increases
Solution Approach 1:
The patent applies preliminary action by performing partial verification of the first group of logic states and discarding corresponding data before completing programming of all logic states. This reduces programming duration while maintaining programming accuracy through the recovery mechanism that ensures data can be restored if programming failure occurs.
Solution Approach 2:
The system implements discarding and recovering by allowing early disposal of data after partial verification, reducing programming duration. Programming accuracy is maintained because the recovery mechanism ensures that if programming fails, the original data can be restored, thus resolving the contradiction between speed and accuracy.
Data Source
AI summary
A method of cache programming of a NAND flash memory in a triple-level-cell (TLC) mode is provided. The method includes discarding a lower page of a first programming data from a first set of data latches in a plurality of page buffers when a first group of logic states are programmed and verified. The page buffers include the first, second and third sets of data latches configured to store the lower page, a middle page and an upper page of programming data, respectively. The method also includes uploading a lower page of second programming data to a set of cache latches, transferring the lower page of the second programming data from the set of cache latches to the second set of data latches after the discarding the middle page of the first programming data, and uploading a middle page of the second programming data to the set of cache latches.