NAND Memory Channel Boosting via Segmented Isolation
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Solution Overview
Problem
Conventional channel boosting techniques are inadequate in preventing program disturb in non-volatile memory as channel lengths decrease, leading to increased leakage and disturb effects due to high electric fields and hot carriers.
Innovation Solution
The introduction of multiple isolation areas along the NAND memory string to create separate boosting regions, where appropriate pass voltages are applied to reduce current leakage and alleviate gate-induced drain leakage, particularly at the edges of memory regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional channel boosting techniques are used, then programming operation can be performed, but program disturb effects increase as channel lengths decrease
Solution Approach 1:
The channel is divided into multiple separate boosting regions by introducing isolation areas (grounded memory elements) between adjacent boosting regions. This segmentation prevents hot carrier leakage from one boosting region to another, thereby reducing program disturb effects while maintaining necessary channel boosting for programming operations.
Solution Approach 2:
Isolation areas consisting of grounded memory elements are introduced as intermediary regions between adjacent boosting regions. These isolation areas act as mediators that block the propagation of hot carriers and reduce electric field interference between neighboring boosting regions, thereby mitigating program disturb effects.
2Reliability
If isolation areas are introduced to reduce program disturb, then reliability improves, but device complexity increases
Solution Approach 1:
The isolation areas are formed using existing memory elements within the NAND string structure itself, rather than requiring additional external components or complex circuitry. By grounding selected memory elements, the structure leverages its own components to provide isolation functionality, thereby reducing program disturb without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces program disturb effects by maintaining adequate channel boosting and minimizing leakage, even in shorter channel lengths, thereby enhancing the reliability of programming operations.
Implementation Method 1
The threshold voltage Vt of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate
Implementation Method 2
causing electrons from the channel of the memory element to be injected into the floating gate
Implementation Method 3
electrons from the channel of the memory element to be injected into the floating gate
Implementation Method 4
The floating gate cap be used to store two ranges of charges, and therefore, each memory element can have two possible states
Data Source
AI summary
Non-volatile storage elements are programmed in a manner that reduces program disturb, particularly at the edges storage elements strings, by using modified pass voltages. In particular, during the programming of a selected storage element, an isolation voltage is applied to a storage element proximate to the selected storage element thereby electrically dividing the channel associated with the storage elements into two isolated areas. Additional isolated areas are formed remotely from the selected storage element by applying the isolation voltage to other remote storage elements. The isolated channel regions associated with the storage elements are then boosted with different pass voltages in order to alleviate the effects of program disturb. Thus, a standard pass voltage is applied to storage elements immediately adjacent to the selected storage element, and a lower pass voltage is applied to storage elements remote from the selected storage element. In one preferred embodiment, a higher pass voltage is applied to storage elements immediately adjacent the selected storage element on the side having previously programmed storage elements. These techniques reduce the leakage of charge from adjacent boosted channel regions caused by gate induced drain leakage at the source select line and the drain select line, as well as from isolation word lines, thereby reducing program disturb effects.