3D NAND Channel Contact Structure for Lower Contact Resistance
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Solution Overview
Problem
Semiconductor storage devices, such as NAND flash memory, face challenges in achieving low channel contact resistance, which affects their performance and efficiency in data storage operations.
Innovation Solution
The semiconductor storage device incorporates a semiconductor-containing layer with specific structural configurations, including a first portion on the upper end of a pillar, a second portion contacting the first portion and extending along a second wiring layer, and a third portion extending perpendicular to the first direction, with a metal surface on the upper surface of the third portion, and insulating layers between these portions and the wiring layers, to reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor storage devices are used, then manufacturing is simpler, but channel contact resistance is high
Solution Approach 1:
The semiconductor-containing layer is divided into three distinct portions (first, second, and third portions) with different orientations and functions. The first portion is on the upper end of the pillar, the second portion extends along the second wiring layer, and the third portion extends in a direction crossing the second direction. This segmentation allows each portion to be optimized for its specific function, reducing channel contact resistance while maintaining manufacturability.
Solution Approach 2:
The invention transitions from a conventional planar contact structure to a three-dimensional multi-directional structure. The semiconductor-containing layer extends in multiple directions (first direction along the pillar, second direction along the wiring layer, and third direction crossing the second direction), creating a multi-dimensional contact architecture that reduces resistance without excessive manufacturing complexity.
2Reliability
If the semiconductor-containing layer is extended in multiple directions, then contact resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
An insulating layer is introduced as an intermediary between the semiconductor-containing layer and the second wiring layer. This insulating layer facilitates precise alignment and separation of the multi-directional structures, enabling the complex three-portion semiconductor configuration to be manufactured with controlled precision while maintaining low contact resistance.
Solution Approach 2:
Different regions of the semiconductor-containing layer are assigned different orientations and functions. The first portion contacts the pillar vertically, the second portion extends horizontally along the wiring layer, and the third portion crosses the second direction. This local differentiation optimizes electrical connection in each region while the insulating layer ensures manufacturability through localized separation.
3Reliability
If insulating layers are added between portions and wiring layers, then conductor penetration is prevented, but device complexity increases
Solution Approach 1:
The insulating layer serves as a mediator positioned between the semiconductor-containing layer portions and the second wiring layer. It prevents conductor penetration while maintaining the multi-directional semiconductor structure for low resistance. The insulating layer is strategically placed only where needed to separate the semiconductor portions from the wiring layer, balancing protection with structural simplicity.
Data Source
AI summary
A semiconductor storage device includes first wiring layers stacked along a first direction, a first pillar including a first semiconductor layer and extending along the first direction through the first wiring layers, a second wiring layer disposed above the first pillar in the first direction and extending along a second direction perpendicular to the first direction, a semiconductor-containing layer including a first portion disposed on an upper end of the first pillar in the first direction, a second portion contacting the first portion and formed along the second wiring layer, and a third portion contacting an upper end of the second portion and extending along a third direction perpendicular to the first direction and crossing the second direction, and a first insulating layer between each of the first and second portions of the semiconductor-containing layer and the second wiring layer. An upper surface of the third portion contains a metal.