Vertical NAND Channel Structure With Sidewall Doping for Select Gates
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Solution Overview
Problem
Existing integrated structures face challenges in achieving desired doping levels within the gated region of select devices in NAND architecture, particularly in vertically-stacked memory cells, due to difficulties in out-diffusion of dopant to specific locations.
Innovation Solution
The development of new integrated structures with conductively-doped semiconductor material directly against the lower sidewalls of the channel material, allowing for uniform dopant out-diffusion into the channel material, forming both heavily-doped and lightly-doped regions to achieve non-leaky 'OFF' characteristics and GIDL-induced hole generation for block erase of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional out-diffusion methods are used to dope the channel material, then the doping process is simpler, but the desired doping levels and locations cannot be achieved
Solution Approach 1:
The channel material is divided into distinct doped and undoped regions along its length. The doped region is positioned to overlap with the select device gate, while the undoped region extends upward. This segmentation enables precise control of doping levels at specific locations to achieve both non-leaky OFF characteristics and GIDL-induced hole generation.
Solution Approach 2:
Different regions of the channel material are assigned different doping qualities. The lower portion overlapping the select device gate is heavily doped to provide non-leaky OFF characteristics, while the upper portion remains lightly doped or undoped. This local differentiation of doping quality enables simultaneous achievement of low leakage and efficient hole generation.
2Reliability
If the channel material is heavily doped to provide non-leaky OFF characteristics, then the OFF characteristics improve, but the ability to generate holes via GIDL decreases
Solution Approach 1:
The channel material is segmented into a heavily-doped lower region overlapping the select device gate to ensure non-leaky OFF characteristics, and a lightly-doped or undoped upper region that extends upward. This segmentation allows each region to fulfill its specific function: the doped region provides low leakage, while the undoped region enables efficient hole generation via GIDL when the select device is OFF.
Solution Approach 2:
Different doping qualities are applied to different portions of the channel material. The lower portion has high doping concentration to suppress leakage current, while the upper portion has low or zero doping to facilitate hole generation. This local quality differentiation resolves the contradiction between achieving low leakage and maintaining hole generation capability.
3Manufacturing precision
If conductively-doped semiconductor material is placed directly against lower sidewalls of channel material, then uniform dopant out-diffusion is achieved, but the manufacturing process becomes more complex
Solution Approach 1:
Conductively-doped semiconductor material is placed against the lower sidewalls of the channel material structure in advance, before the dopant out-diffusion process begins. This preliminary positioning of dopant sources ensures uniform dopant distribution throughout the channel material during subsequent thermal processing, eliminating the need for complex multi-step doping procedures.
Solution Approach 2:
The conductively-doped semiconductor material serves as a self-contained dopant source that automatically diffuses dopant uniformly into the channel material through thermal processing. This self-service mechanism eliminates the need for external dopant introduction steps, simplifying the overall manufacturing process while achieving uniform dopant distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of doping across an array of select devices, ensuring desired 'OFF' characteristics and efficient block erase of memory cells, improving the performance and reliability of NAND architecture.
Implementation Method 1
allowing for uniform dopant out-diffusion into the channel material, forming both heavily-doped and lightly-doped regions
Implementation Method 2
A gating structure of a transistor may be utilized to provide gate-induced drain leakage (GIDL) which generates the holes utilized for block-erase of the memory cells
Data Source
AI summary
Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.