3D NAND Channel Wiring Layout for Hydrogen Repair and Skew Control

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Solution Overview

Problem

Semiconductor devices face challenges in maintaining electrical characteristics due to damage from deposition, etching, and thermal processes, which degrade the memory channel's performance, and existing solutions do not effectively address noise-related skew issues, leading to increased costs and time in modifying circuit patterns.

Innovation Solution

Incorporating a dummy wiring structure that connects to the common source line driver, allowing hydrogen to cure damaged polysilicon channels and improving electrical characteristics, while also enabling easier skew correction by connecting a portion of the dummy wiring to the upper wiring structure electrically connected to the CSL driver.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If deposition, etching, and thermal processes are used to form structures, then device functionality is achieved, but the memory channel structure is damaged and electrical properties are degraded

Engineering Contradiction:
Improvestructure formationVSAvoidelectrical properties of channel
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The dummy wiring structure is formed before the memory channel structure in the manufacturing process. This preliminary formation allows the dummy wiring to be in place to provide hydrogen during subsequent processing steps, preventing channel damage before it occurs during deposition, etching, and thermal processes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy wiring structure acts as an intermediary that provides hydrogen to the memory channel structure during processing. The dummy wiring serves as a hydrogen source that migrates hydrogen atoms to the channel region, curing damaged polysilicon and maintaining electrical properties without interfering with the normal device operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If circuit patterns are modified to correct noise-related skew, then skew issues are addressed, but cost and time increase

Engineering Contradiction:
Improvenoise-related skew correctionVSAvoidtime and cost for modification
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The dummy wiring structure is preliminarily formed with specific connectivity configurations that inherently provide noise immunity and skew correction capabilities. By pre-configuring the dummy wiring to connect to certain wiring structures but not others, the design built-in protection against noise-related skew without requiring post-manufacturing modifications.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy wiring structure automatically provides noise immunity and skew correction functions through its inherent design and hydrogen provision mechanism. The system self-corrects channel damage and mitigates noise effects without requiring external intervention or additional processing steps to modify circuit patterns.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enhances the electrical characteristics of the memory channel and reduces the cost and time required to address noise-related skew issues by using hydrogen to cure channel damage and simplifying the modification of circuit patterns.

Implementation Method 1

hydrogen that moves through a dummy wiring structure that connects the channel connection pattern to the channel can cure the channel

Methodology Applied
Scientific EffectHydrogen diffusion: Diffusion

Data Source

PatentUS12057391B2Semiconductor device and massive data storage system including the same
Publication Date: 2024.08.06 SAMSUNG ELECTRONICS CO LTD
  • US12057391B2 patent drawing
  • US12057391B2 patent drawing
  • US12057391B2 patent drawing

AI summary

A semiconductor device includes a CSL driver on a substrate, a CSP on the CSL driver, a gate electrode structure on the CSP and including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate, a memory channel structure on the CSP and extending through the gate electrode structure and is connected to the CSP, a first upper wiring structure contacting an upper surface of the CSP, a first through via extending through the CSP in the first direction and is electrically connected to the first upper wiring structure and the CSL driver but does not contact the CPS, and a dummy wiring structure contacting the upper surface of the CSP but is not electrically connected to the CSL driver.