Vertical NAND Channel Ends for Reliable Source Contact
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Solution Overview
Problem
The degradation of CMOS devices due to collateral thermal cycling and hydrogen diffusion during the manufacture of three-dimensional memory devices poses challenges for the performance of support circuitry in vertical NAND strings, necessitating high-performance support circuitry solutions.
Innovation Solution
A semiconductor structure with a memory die featuring an alternating stack of insulating and electrically conductive layers, a dielectric spacer layer, and a memory opening fill structure including a dielectric core and a vertical semiconductor channel with a hollow portion, along with a source layer contacting the pillar portion of the channel, is developed. This structure is formed through a method involving the deposition of sacrificial material layers, conversion to electrically conductive layers, and removal of the carrier substrate to create a high-performance support circuitry for three-dimensional memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional manufacturing processes are used for three-dimensional memory devices, then production can proceed with standard methods, but CMOS support circuitry degrades due to collateral thermal cycling and hydrogen diffusion
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: forming the alternating stack structure first, then creating memory openings, and finally forming source contacts. This segmentation allows independent optimization of each stage, enabling the use of conventional deposition and etching methods while protecting CMOS circuitry by controlling thermal and chemical exposure in separate process windows.
Solution Approach 2:
The patent introduces dielectric layers and spacer structures as intermediary elements between the memory stack and source contacts. These intermediaries act as protective barriers that prevent direct exposure of CMOS support circuitry to harmful thermal cycling and hydrogen diffusion during subsequent processing steps, thereby maintaining CMOS reliability while completing memory device fabrication.
2Device complexity
If source contacts are formed with minimal contact area to the vertical semiconductor channels, then device complexity is reduced, but electrical contact performance deteriorates
Solution Approach 1:
The patent transitions from planar contact geometry to three-dimensional vertical contacts that extend through the alternating stack. By utilizing the vertical dimension, the source contacts achieve sufficient electrical contact area with the vertical semiconductor channels without increasing lateral footprint or processing complexity. The contacts follow the vertical architecture naturally, making the enhanced contact area an inherent result of the 3D structure rather than an added complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides enhanced electrical contact and improved performance of support circuitry in three-dimensional memory devices by ensuring a minimum contact area between the source layer and the vertical semiconductor channels, thereby addressing the degradation issues associated with CMOS devices.
Implementation Method 1
forming a dielectric oxide spacer by converting a surface portion of the semiconductor material layer into a dielectric oxide of a semiconductor material
Data Source
AI summary
A memory die includes an alternating stack of insulating layers and electrically conductive layers, a dielectric spacer layer underlying the alternating stack, memory opening vertically extending through the alternating stack, and through the dielectric spacer layer, a memory opening fill structure located in the memory opening and including a dielectric core, a vertical semiconductor channel having a hollow portion which surrounds the dielectric core and a pillar portion which does not surround the dielectric core, and a memory film, and a source layer located under the dielectric spacer layer and contacting the pillar portion of the vertical semiconductor channel.