Vertical NAND Charge Trap Layer With Nanocrystals for Charge Retention
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Solution Overview
Problem
In vertical NAND flash memory devices, the increase in stacked memory cells and decrease in cell height lead to lateral charge spreading, deteriorating charge retention due to charge movement between cells, which affects memory density and reliability.
Innovation Solution
A vertical NAND flash memory device is developed with a charge trap layer comprising amorphous metal oxynitride and spatially discrete nitride nanocrystals, which improves retention by minimizing charge movement through increased trap energy and density, and by inserting specific nitride/oxide layers to inhibit crystallization and enhance dielectric constant and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked memory cells is increased and cell height is decreased to improve memory density, then memory integration is improved, but lateral charge spreading occurs and charge retention deteriorates
Solution Approach 1:
The charge trap layer is designed with spatially discrete nanocrystals distributed within an amorphous metal oxynitride matrix, creating localized charge trapping sites with different properties from the surrounding matrix. This local quality differentiation allows charges to be confined at specific nanocrystal locations while the amorphous matrix provides overall structural stability and prevents lateral charge spreading between adjacent memory cells.
Solution Approach 2:
The charge trap layer employs a composite structure combining amorphous metal oxynitride material with dispersed nanocrystals. This composite material integrates the benefits of both components: the amorphous metal oxynitride provides a stable matrix with appropriate dielectric properties, while the embedded nanocrystals create discrete charge trapping centers that enhance charge retention without causing lateral charge spreading.
2Ease of manufacture
If a conventional charge trap layer structure is used, then manufacturing is simpler, but charge movement between cells occurs and retention is poor
Solution Approach 1:
The charge trap layer utilizes changes in material parameters by employing amorphous metal oxynitride with specific compositional ratios and incorporating nanocrystals of controlled size and distribution. These parameter changes create a charge trap layer with optimized electrical properties that prevent charge movement between cells while maintaining manufacturability through established thin film deposition and heat treatment processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves charge retention and memory window characteristics by suppressing charge movement, enhancing the reliability and operating characteristics of the vertical NAND flash memory device.
Implementation Method 1
a charge trap layer which includes: a matrix; and a plurality of nanocrystals which are provided in the matrix, the plurality of nanocrystals including nitride
Implementation Method 2
a matrix including amorphous metal oxynitride
Implementation Method 3
during subsequent heat treatment, the added nitrogen/oxide layers inhibit crystallization of the existing charge trap layer, resulting in the formation of an amorphous thin film
Data Source
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AI summary
A vertical NAND flash memory device and an electronic apparatus including the same are provided. The vertical NAND flash memory device includes a plurality of cell arrays. Each of the plurality of cell arrays includes a channel layer, a charge trap layer, and a plurality of gate electrodes provided on the charge trap layer. The charge trap layer includes a matrix including amorphous metal oxynitride and nanocrystals dispersed in the matrix and including nitride having semiconductor characteristics.