Vertical NAND Charge Trap Layer Nanostructures for Charge Retention
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Solution Overview
Problem
In vertical NAND flash memory devices, the increase in the number of stacked memory cells and decrease in cell height leads to charge mobility issues, deteriorating charge retention characteristics.
Innovation Solution
A vertical NAND flash memory device with a charge trap layer comprising a base and nanostructures distributed in the base, where the nanostructures have a higher trap density and lower band gap than the base material, formed through spinodal decomposition of a mixture layer by atomic layer deposition, enhancing charge retention and device integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked memory cells is increased and cell height is decreased to achieve higher integration, then device integration is improved, but charge mobility increases causing charge retention characteristics to deteriorate
Solution Approach 1:
The charge trap layer is designed with non-uniform composition featuring nanoscale clusters of high-k material distributed within a dielectric matrix. This local quality variation creates regions with different trap densities and energy levels, enabling effective charge retention despite reduced cell heights and increased stacking density.
Solution Approach 2:
The charge trap layer employs a composite structure combining high-k dielectric material clusters with a surrounding dielectric matrix material. This composite approach leverages the high trap density of the high-k material while using the matrix to provide structural stability and control charge transport, effectively managing charge retention in highly integrated vertical NAND structures.
2Ease of manufacture
If conventional charge trap layers are used in highly integrated vertical NAND, then manufacturing is simpler, but charge mobility causes poor charge retention
Solution Approach 1:
The charge trap layer's physical and chemical parameters are optimized by controlling cluster size (2-20 nm), cluster concentration (10^18 to 10^20 clusters/cm³), and composition ratios. These parameter changes enable effective charge trapping while maintaining compatibility with existing manufacturing processes for forming the charge trap layer within the vertical NAND structure.
3Ease of manufacture
If uniform charge trap layer is used, then manufacturing is easier, but surface roughness control becomes difficult affecting device uniformity
Solution Approach 1:
The charge trap layer utilizes local quality variations with nanoscale clusters distributed throughout the dielectric matrix. This approach allows the overall layer to maintain good planarity for manufacturing while the local cluster structures provide the necessary charge trapping functionality, achieving both ease of manufacture and surface uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves charge retention characteristics and device uniformity by reducing charge mobility, allowing for higher integration with narrower conductive layer gaps and more uniform surface roughness.
Implementation Method 1
forming a charge trap layer on an inner wall of the channel hole and inducing spinodal decomposition by performing a heat treatment process on the mixture material layer
Implementation Method 2
inducing spinodal decomposition by performing a heat treatment process on the mixture material layer
Data Source
AI summary
A vertical NAND flash memory device and a method of manufacturing the same are provided. The vertical NAND flash memory device includes a charge trap layer arranged on an inner wall of a channel hole vertically formed on a substrate. The charge trap layer includes nanostructures distributed in a base. The nanostructures may include a material having a trap density of about 1×1019 cm−3 to about 10×1019 cm−3, and the base may include a material having a conduction band offset (CBO) of about 0.5 eV to about 3.5 eV with respect to the material included in the nanostructures.