Vertical NAND Charge Trap Layer With Ga/In for Charge Retention
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Solution Overview
Problem
In vertical NAND flash memory devices, lateral charge spreading due to increased stacked stages and decreased memory cell height deteriorates charge retention, affecting the performance of memory cells.
Innovation Solution
Incorporating a charge trap layer made of silicon oxynitride with metal, such as Ga or In, which is uniformly distributed or layered, to enhance trap energy and density, thereby improving charge retention and allowing for higher integration by reducing the distance between gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked stages is increased to achieve higher integration, then storage capacity is improved, but lateral charge spreading occurs which deteriorates charge retention
Solution Approach 1:
The patent applies local quality by introducing metal elements (Ga or In) specifically into the charge trap layer at controlled concentrations (0.5-20 at%). This creates a localized modification of the charge trap layer's properties, enhancing trap energy and density precisely where needed to prevent lateral charge spreading, while maintaining the overall vertical stacking structure for high integration.
Solution Approach 2:
The patent employs composite materials by combining metal elements (Ga or In) with silicon oxynitride in the charge trap layer. This composite structure creates a material with enhanced trap energy and density, effectively addressing the charge retention issue while preserving the vertical NAND architecture's high storage capacity.
2Volume of moving object
If memory cell height is decreased to accommodate more stacked stages, then integration density is improved, but charge retention deteriorates due to increased lateral charge spreading
Solution Approach 1:
The patent applies parameter changes by modifying the charge trap layer's composition parameters - specifically incorporating metal elements at controlled concentrations (0.5-20 at%). This changes the physical and electrical parameters of the charge trap layer, increasing trap energy and density, which compensates for the reduced memory cell height and prevents lateral charge spreading in highly integrated structures.
Solution Approach 2:
The patent uses composite materials by creating a charge trap layer that combines metal elements (Ga or In) with silicon oxynitride. This composite material provides enhanced charge trapping capability that maintains reliability even when memory cell height is reduced to achieve higher integration density.
3Reliability
If metal content in charge trap layer is increased to improve charge retention, then trap energy and density are enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies partial action by introducing metal elements at optimized partial concentrations (0.5-20 at%) rather than high concentrations. This partial incorporation is sufficient to enhance trap energy and density for improved charge retention, while avoiding the need for extremely precise manufacturing control that would be required for higher metal content.
Data Source
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AI summary
A vertical NAND flash memory device may include a plurality of cell arrays (110). Each of the plurality of cell arrays may include a channel layer (129), a charge trap layer (125) on the channel layer, and a plurality of gate electrodes (121) on the charge trap layer. The charge trap layer may include silicon oxynitride comprising a metal. The metal may include at least one of Ga or In.