NAND Memory Check Biasing for Channel Failure Detection
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Solution Overview
Problem
The increasing integration and miniaturization of nonvolatile memory devices lead to reliability issues due to potential channel failures and threshold voltage errors, which can result in data damage and reduced storage device reliability.
Innovation Solution
A nonvolatile memory device is designed with a check operation mechanism that applies specific voltage sequences to bit lines, word lines, and selection lines to detect channel failures and threshold voltage errors, allowing for the distinction between short-circuited channels and threshold voltage errors, thereby improving device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the degree of integration of the storage device is increased to reduce manufacturing costs, then manufacturing cost decreases, but reliability deteriorates due to scale-down and structure change causing channel failures and threshold voltage errors
Solution Approach 1:
The patent performs preliminary detection of channel failures and threshold voltage errors through specific check operations before data storage operations. By applying turn-off voltage to ground selection line and turn-on voltage to string selection line while monitoring bit line voltage changes, the system identifies potential failures in advance, preventing data damage and maintaining reliability despite high integration.
Solution Approach 2:
The patent implements feedback mechanisms where the page buffer senses voltage changes on bit lines during check operations and provides status information back to the control logic. This feedback loop enables continuous monitoring of cell string health, allowing the system to detect and respond to channel failures and threshold voltage errors, thereby maintaining reliability in highly integrated devices.
2Quantity of substance
If miniaturization is pursued to increase storage capacity, then storage density increases, but detection precision deteriorates due to difficulty in identifying channel failures and threshold voltage errors
Solution Approach 1:
The patent applies local quality by performing targeted check operations on specific cell strings rather than uniform scanning. By selectively applying voltages to ground selection lines and string selection lines and monitoring specific bit lines, the system achieves precise local detection of channel failures and threshold voltage errors in miniaturized structures where such failures are difficult to identify.
Solution Approach 2:
The patent utilizes parameter changes by varying voltage levels applied to different lines (ground selection line, string selection line, bit lines) to create detectable voltage changes that indicate failures. The check operation employs specific voltage sequences that cause measurable parameter changes in the bit line voltages, enabling precise detection of channel failures and threshold voltage errors despite miniaturization.
3Reliability
If check operations are performed to improve reliability, then device reliability improves, but operation time increases due to additional voltage application and sensing periods
Solution Approach 1:
The patent implements periodic action by dividing the check operation into distinct time periods: a first period for applying bias voltages to bit lines and selection lines, and a second period for sensing voltage changes. This periodic structure allows systematic detection of channel failures and threshold voltage errors while managing operation time through organized sequential steps rather than continuous monitoring.
Solution Approach 2:
The patent applies skipping by rapidly transitioning between voltage states during the check operation. The control logic quickly applies turn-off and turn-on voltages to selection lines, and the page buffer rapidly senses voltage changes on bit lines. This rushed-through approach minimizes the duration of each check operation while still detecting failures, thereby reducing the time penalty for reliability enhancement.
Data Source
AI summary
Disclosed is a nonvolatile memory device, which includes a memory cell array including cell strings, a row decoder connected with a ground selection transistor of each of the cell strings through a ground selection line, connected with memory cells of each of the cell strings through word lines, and connected with a string selection transistor of each of the cell strings through a string selection line, and a page buffer connected with the cell strings through bit lines. In a first period of a check operation, the page buffer applies a first bias voltage to the bit lines, and the row decoder applies a turn-off voltage to the ground selection line, a turn-on voltage to the string selection line, and a first check voltage to the word lines. In a second period of the check operation, the page buffer senses first changes of voltages of the bit lines.