NAND Memory Programming with Checkpoint Verify and Blind Pulses
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in accurately programming threshold voltage ranges, leading to inefficiencies in programming speed and distribution tightness.
Innovation Solution
Implementing predictive programming with reduced verify operations by applying blind program pulses and adjusting bit line voltages to memory cells, particularly those susceptible to over-programming, while skipping verify steps for non-checkpoint cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional programming with verify operations is used, then programming accuracy is improved, but programming speed deteriorates
Solution Approach 1:
The patent segments the memory array into checkpoint and non-checkpoint portions, applying different programming strategies to each. Checkpoint memory cells receive traditional programmed verify programming for accuracy, while non-checkpoint memory cells receive blind programming for speed, resolving the contradiction between programming accuracy and speed.
Solution Approach 2:
The patent applies different programming qualities to different regions: verified programming with multiple verify operations is applied to checkpoint portions where accuracy is critical, while unverified blind programming is applied to non-checkpoint portions where speed is prioritized, allowing simultaneous optimization of both accuracy and speed in different locations.
2Productivity
If blind programming is used for all memory cells, then programming speed is improved, but programming precision deteriorates
Solution Approach 1:
The patent divides the memory array into checkpoint and non-checkpoint portions, applying blind programming only to non-checkpoint memory cells while using traditional verified programming for checkpoint memory cells. This segmentation allows the system to achieve high programming speed overall while maintaining threshold voltage distribution tightness through verified programming of the checkpoint portion.
Solution Approach 2:
The checkpoint memory cells act as an intermediary reference that ensures distribution tightness. By programming a smaller checkpoint portion with high precision and using it as a reference, the system can afford to use faster blind programming on the remaining non-checkpoint cells while still achieving acceptable overall precision.
3Reliability
If verify operations are performed on all memory cells, then programming accuracy is improved, but time consumption increases
Solution Approach 1:
The patent extracts the verify operation from the entire memory array and applies it only to the checkpoint portion. By taking out the time-consuming verify operations and limiting them to a small subset of checkpoint memory cells, the system maintains programming reliability for the critical checkpoint region while dramatically reducing overall time consumption through blind programming of the non-checkpoint region.
Solution Approach 2:
The patent applies verify operations partially rather than excessively to all cells. By performing verify operations on only the checkpoint portion (partial action) rather than all memory cells (excessive action), the system achieves sufficient programming reliability for the critical checkpoint cells while minimizing time loss through blind programming of the remaining cells.
4Device complexity
If uniform programming is applied to all word lines, then simplicity is maintained, but over-programming susceptibility increases
Solution Approach 1:
The patent applies different programming characteristics to different word lines based on their susceptibility to over-programming. Word lines identified as susceptible to over-programming have their verify low voltages adjusted to be more conservative, while non-susceptible word lines can use standard verify low voltages. This local quality approach maintains reliability by protecting vulnerable word lines while avoiding unnecessary complexity in the overall programming control.
Solution Approach 2:
The patent makes the programming parameters dynamic by adjusting verify low voltages based on word line susceptibility characteristics. Rather than using a static uniform verify low voltage for all word lines, the system dynamically selects appropriate verify low voltages based on each word line's over-programming susceptibility, improving reliability without significantly increasing control complexity.
Data Source
AI summary
A memory apparatus includes memory cells and a control means configured to adjust at least one of blind program pulses applied to word lines connected to the memory cells and bit line voltages applied to bit lines coupled to the memory cells in response to determining one of the word lines connected to the memory cells being programmed is susceptible to over-programming. The control means programs non-checkpoint ones of the memory cells associated with a checkpoint state to a verify low voltage for the checkpoint state and programs the non-checkpoint ones of the memory cells to respective non-checkpoint states associated with the checkpoint state by applying the blind program pulses to each non-checkpoint one of the memory cells without verifying whether the non-checkpoint ones of the memory cells have reached their respective non-checkpoint states while applying the bit line voltages to the bit lines associated therewith.