NAND Partial Checksum Test Read for SSD Error Screening

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

NAND-type flash memory in SSDs face challenges with reduced lifespan and decreased data reliability due to fabrication process limits, necessitating improved error correction for enhanced data integrity.

Innovation Solution

A hybrid test read scheme using in-NAND partial checksum and actual test reads, employing a control circuit to compare partial checksums with thresholds and perform additional test reads when necessary to determine the number of failed bits in codeword sequences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional test read schemes are used to ensure data reliability, then data integrity is improved, but power consumption and processing time increase due to transferring data to system-on-a-chip

Engineering Contradiction:
Improvedata integrityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the test read operation into two parts: a partial checksum calculation performed inside the memory device using only a subset of parity check equations, and a full test read performed only when necessary. This segmentation allows the memory device to perform basic error detection locally without transferring all data to the system-on-a-chip, thereby reducing power consumption while maintaining data integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by calculating only a partial checksum using a subset of parity check equations instead of performing a complete test read. This partial checksum provides sufficient information to determine if a test read is necessary, avoiding the excessive action of transferring and fully processing all data when the partial check is sufficient.

Inventive Principle:
Principle #16Partial or excessive action

2Speed

If partial checksum calculation is performed inside memory device, then processing speed is improved, but measurement precision of bit error rate estimation decreases

Engineering Contradiction:
Improveprocessing speedVSAvoidbit error rate estimation accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent implements a feedback mechanism where the partial checksum result is used to determine whether a full test read is necessary. If the partial checksum indicates potential errors, the system performs a full test read to obtain accurate bit error rate measurement. This feedback loop ensures that speed is improved when partial checksum is sufficient, while precision is maintained when needed.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent makes the error detection process dynamic by adjusting the level of checking based on the partial checksum result. The system transitions from a static full test read to a dynamic approach where the depth of testing varies based on initial findings, allowing optimization between processing speed and measurement precision.

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If full test read is performed on all data, then measurement precision of bit error rate is improved, but device complexity and processing time increase

Engineering Contradiction:
Improvebit error rate measurement accuracyVSAvoidprocessing complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the error detection process into a first stage (partial checksum calculation) and a second stage (full test read only when necessary). This segmentation reduces the complexity of always performing full test reads while maintaining the option to do so when needed, thereby reducing overall processing complexity and time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by performing only the necessary level of testing. Instead of always performing excessive full test reads, the system performs partial checksum calculation first, then applies full testing only when the partial result indicates a need, thereby reducing unnecessary complexity and processing time.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20260080963A1Hybrid test read scheme using in-NAND partial checksum
Publication Date: 2026.03.19 SK HYNIX INC
  • US20260080963A1 patent drawing
  • US20260080963A1 patent drawing
  • US20260080963A1 patent drawing

AI summary

A memory device and method for a hybrid test read scheme using two thresholds based on in-NAND partial checksum and normal test read. The memory device includes: at least one super block including memory blocks; a control circuit to perform a first test read on a codeword sequence; and a partial checksum calculator to calculate a partial checksum on a syndrome sequence based on the codeword sequence and a subset matrix. The control circuit compares the partial checksum with first and second thresholds. When the partial checksum is less than the first threshold, it is determined that the codeword sequence is clean. When the partial checksum is greater than the second threshold, it is determined that the codeword sequence is noisy. When the partial checksum is in between the first and second thresholds, a second test read by a controller is performed on the codeword sequence.