NAND Chip-Kill Recovery Using Concatenated ECC Wordlines
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Solution Overview
Problem
Existing chip-kill parity systems in NAND flash memory devices fail to recover data when decoding errors exceed the error correction capability of Low-Density Parity-Check (LDPC) decoders, leading to incomplete protection against memory failures.
Innovation Solution
A novel chip-kill scheme is introduced, where additional parity bits are generated and stored in a separate wordline, allowing for the use of a higher error correction capability ECC code to decode failed wordlines and bitlines, even when errors surpass the original decoder's capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional chip-kill parity is used for error correction, then the system can handle single wordline failures, but it fails to recover when multiple wordlines fail or when errors exceed LDPC decoder capability
Solution Approach 1:
The patent segments the error correction task into two stages: first, standard LDPC decoding for normal operation; second, a fallback concatenated code decoding mechanism activated only when LDPC decoding fails. This segmentation allows the system to maintain high reliability for common cases while having enhanced capability for rare failure scenarios without always incurring the full complexity overhead.
Solution Approach 2:
The patent performs preliminary action by pre-calculating and storing the XOR of data bits from multiple wordlines during the write operation. This pre-computed parity information is stored in dedicated parity wordlines, so that when failures occur, the recovery process can immediately utilize this pre-prepared data without needing to perform complex real-time calculations during read operations.
2Reliability
If more parity bits are added to increase error correction capability, then more errors can be corrected, but the storage capacity and code rate decrease
Solution Approach 1:
The patent applies partial action by implementing error correction enhancement only in the specific scenario where LDPC decoding fails. Instead of always using the more complex concatenated code scheme which would reduce storage capacity, the system uses standard LDPC decoding for normal operation and only activates the additional parity bits from concatenated codes when needed. This allows the system to have enhanced error correction capability available without permanently sacrificing storage capacity.
Solution Approach 2:
The patent uses an intermediary approach by introducing a hybrid decoding mechanism that combines LDPC decoding with concatenated code decoding. The system first attempts standard LDPC decoding, and only when that fails does it invoke the concatenated code recovery process using pre-stored parity bits. This intermediary strategy allows the system to maintain high storage capacity while having the option to correct more errors when necessary.
3Reliability
If concatenated codes with higher error correction capability are used, then more failed wordlines can be recovered, but the decoding complexity and processing time increase
Solution Approach 1:
The patent implements a dynamic decoding approach where the system adapts its decoding strategy based on the actual failure conditions. The decoding process is structured as a decision tree: first attempt fast LDPC decoding, and only if that fails, activate the more time-consuming concatenated code decoding. This dynamic approach ensures that the system incurs the time penalty for complex decoding only when absolutely necessary, maintaining fast performance for the majority of read operations.
Solution Approach 2:
The patent uses an intermediary decoding strategy that acts as a bridge between fast but limited LDPC decoding and slow but powerful concatenated code decoding. The system first tries the fast LDPC approach, and only when that intermediary step fails does it proceed to the full concatenated code recovery process. This two-stage intermediary approach minimizes average decoding time while maintaining the capability to handle severe failures.
Data Source
AI summary
Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when writing data to a superblock of the memory, a wordline of the superblock stores “D+P” parity bits that protect “D” data bits of a codeword having a length of “2D+P.” Other wordlines of the superblock store codewords each having a length of “D+P” (e.g., “D” data bits and “P” parity bits). If the decoding of any of these codewords of length “D+P” fails, the “D+P” parity bits are used to re-decode the failed wordline.