Stacked NAND Chip Bonding Pad Layout for Kerf Region Reliability
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently bonding stacked NAND flash memory chips, leading to issues such as bonding failures, chip chipping, and uneven polishing during manufacturing processes due to non-uniform distribution of bonding pads.
Innovation Solution
A staggered arrangement of bonding pads in the kerf regions of semiconductor devices, with a coverage ratio between 5% and 15%, enhances the bonding process by reducing variations in polishing rates and minimizing chip chipping during dicing, while maintaining electrical uncoupling of dummy pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding pads are arranged in kerf regions to improve bonding process, then bonding reliability is improved, but polishing uniformity deteriorates due to non-uniform distribution
Solution Approach 1:
The patent applies local quality by arranging bonding pads with different coverage ratios in different regions of the kerf area. Specifically, the first bonding pad has a coverage ratio of 10% while the second bonding pad has a coverage ratio of 5%, creating non-uniform local distributions that address both bonding reliability and polishing uniformity requirements in different zones.
2Strength
If bonding pads are densely arranged to improve bonding strength, then bonding strength is improved, but chip chipping increases during dicing
Solution Approach 1:
The patent changes the coverage ratio parameter of bonding pads to optimize both bonding strength and reduce chip chipping. By setting coverage ratios between 1% and 20% (with specific embodiments at 10% and 5%), the patent achieves adequate bonding strength while maintaining sufficient spacing to prevent chip chipping during dicing operations.
3Manufacturing precision
If bonding pads are uniformly distributed to improve polishing uniformity, then polishing uniformity is improved, but bonding reliability deteriorates in kerf regions
Solution Approach 1:
The patent applies asymmetry by intentionally creating non-uniform bonding pad distribution in kerf regions. The first and second bonding pads are positioned asymmetrically with different coverage ratios (10% and 5% respectively), which provides enhanced bonding reliability in the kerf area while the overall distribution maintains adequate polishing uniformity across the chip surface.
Data Source
AI summary
According to an embodiment, a semiconductor device includes a first chip including a substrate, and a second chip bonded to the first chip at a first surface. Each of the first chip and the second chip includes an element region, and an end region including a chip end portion. The first chip includes a plurality of first electrodes that are arranged on the first surface in the end region and are in an electrically uncoupled state. The second chip includes a plurality of second electrodes that are arranged on the first surface in the end region, are in an electrically uncoupled state, and are respectively in contact with the first electrodes.