NAND Interface Clock Output With Duty and Phase Correction
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Solution Overview
Problem
Semiconductor integrated circuits face challenges in accurately processing signals due to signal deterioration during transmission, particularly in NAND devices, where corrections in duty and phase by the memory controller may not ensure high accuracy processing by the NAND device.
Innovation Solution
A semiconductor integrated circuit configuration that includes a clock supply circuit generating multiple clock periods, and output circuits that adjust signal duty and phase based on detection within the NAND device, using DDR flip-flop circuits and duty adjustment circuits to correct signals before transmission, ensuring accurate processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller corrects duty and phase of signals, then signal quality is improved, but the accuracy of signal processing in the NAND device is still insufficient
Solution Approach 1:
The patent implements a feedback mechanism where the NAND device detects the actual duty and phase of received signals and communicates correction values back to the memory controller. The memory controller then adjusts its signal output based on this feedback, creating a closed-loop system that continuously optimizes signal quality to ensure accurate processing by the NAND device.
Solution Approach 2:
The patent replaces traditional mechanical/physical signal adjustment methods with a digital control approach. Instead of physically adjusting signal properties, the system uses digital detection of duty and phase values followed by computational correction through control signals, enabling more precise and adaptable signal optimization.
2Productivity
If signal transmission is performed over transmission lines, then data communication is enabled, but signal deterioration occurs during transmission
Solution Approach 1:
The patent applies preliminary action by having the NAND device detect signal characteristics (duty and phase) and communicate correction values back to the memory controller before subsequent data transmission. This allows the memory controller to pre-adjust signal parameters, compensating for transmission line effects before they degrade the signal quality during actual data communication.
Solution Approach 2:
The patent dynamically changes signal parameters (duty cycle and phase) based on detected transmission characteristics. The system measures actual signal properties after transmission and adjusts these parameters in subsequent transmissions to compensate for deterioration, maintaining signal quality despite the presence of transmission lines.
3Measurement precision
If duty adjustment circuits and DDR flip-flop circuits are added, then signal accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the NAND device to perform its own signal quality detection and generate correction values autonomously. The NAND device uses its internal resources to detect duty and phase characteristics and communicates these findings back to the memory controller, eliminating the need for complex external measurement equipment or additional control circuitry.
Solution Approach 2:
The patent achieves multi-functionality by having the NAND device perform both its primary data storage function and secondary signal detection function. The same NAND device that stores data also detects signal duty and phase characteristics, reducing the need for separate dedicated detection circuits and thereby limiting the increase in overall device complexity.
Data Source
AI summary
According to one embodiment, a semiconductor integrated circuit includes a clock supply circuit, a first output circuit, and a second output circuit. The clock supply circuit outputs a first clock and a second clock, the first clock having a first period, the second clock having a second period that is 1/m times the first period. The m is a natural number of 2 or more. The first output circuit outputs a first signal indicating content of data to an outside when a first operation is performed and outputs a second signal having a toggle pattern based on the first clock to the outside when a second operation is performed. The second output circuit outputs an operation clock based on the first clock to the outside when the first operation is performed and outputs a sampling clock based on the second clock to the outside when the second operation is performed.