Memory Interface Clock Scaling Across Multiple NAND Channels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing data throughput in computing systems often exceeds the data bandwidth or communication speed of interfaces connected to non-volatile memory devices, leading to data bottlenecks and degraded performance, particularly in solid-state drives (SSDs) based on flash memories.
Innovation Solution
A memory system with an interface circuit that divides a received clock signal into multiple clock signals based on the number of non-volatile memories, allowing for adaptive operating frequency adjustment to synchronize data exchange between the memory controller and non-volatile memories, thereby enhancing data throughput and system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data throughput is increased to meet computing system demands, then data bandwidth requirement increases, but interface communication speed becomes insufficient causing data bottlenecks
Solution Approach 1:
The interface circuit divides the high-speed data bus into multiple lower-speed data paths, each connected to individual non-volatile memory devices. This segmentation allows the aggregate bandwidth to match the high data throughput requirement while each individual interface operates at achievable speeds.
Solution Approach 2:
Multiple data paths from individual non-volatile memory devices are merged into a single high-speed data bus that interfaces with the computing system. This combining effect achieves high aggregate bandwidth while maintaining manageable individual interface speeds.
2Quantity of substance
If multiple non-volatile memory devices are connected to increase capacity, then data capacity increases, but clock synchronization becomes complex
Solution Approach 1:
The clock signal distribution is segmented into multiple independent paths, with each path connecting the interface circuit to an individual non-volatile memory device. This segmentation simplifies synchronization by providing dedicated clocking for each device rather than requiring complex shared timing.
Solution Approach 2:
The interface circuit serves multiple functions: it acts as a central controller for data exchange, a clock distributor to multiple memory devices, and a serializer/deserializer. This multi-functionality reduces overall system complexity by consolidating control functions in a single component.
3Productivity
If interface circuit operates at maximum frequency to improve performance, then data exchange speed increases, but operational stability decreases
Solution Approach 1:
The interface circuit dynamically adjusts operating frequencies based on the number and configuration of connected non-volatile memory devices. This dynamic adaptation allows the system to operate at maximum performance when conditions permit while maintaining stability when device configurations change or conditions are less optimal.
Solution Approach 2:
The system changes operational parameters including clock frequency and data bus width based on the number of connected memory devices. By adapting parameters to actual hardware configuration, the system achieves optimal performance while maintaining operational stability across different deployment scenarios.
Data Source
AI summary
A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.