NAND Program-Verify Coarse Bitscan for Faster Multi-Level Programming
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in achieving high-speed program operations due to time-consuming inter-pulse verify operations, particularly in multi-level cell formats, which hinder the speed of program completion and the need for improved memory apparatus and methods to address these challenges.
Innovation Solution
The implementation of a memory apparatus and a method of operating the memory apparatus that includes memory apparatus and a method of operating the memory apparatus and a method of operating the memory apparatus that includes memory apparatus and a method of operating the memory apparatus that includes memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, with a control means or controller to program and count failures in a coarse count manner, bypassing detailed counting of sense amplifier tiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If detailed counting of memory cell failures across all sense amplifier tiers is performed during program-verify operations, then measurement precision is improved, but program operation time increases significantly
Solution Approach 1:
The patent segments the sense amplifier structure into multiple tiers (first tier, second tier, etc.) and implements selective counting only for the first tier during program-verify operations. This segmentation allows the system to maintain adequate failure detection capability while significantly reducing the time required for counting operations, as only a portion of the total sense amplifiers are counted in detail during each verify iteration.
2Quantity of substance
If multi-level cell formats are used to increase storage capacity, then quantity of data stored is improved, but program operation speed deteriorates due to time-consuming verify operations
Solution Approach 1:
The patent applies partial action by performing coarse counting (without detailed tier-by-tier analysis) for the majority of sense amplifier tiers, and only performing detailed counting for the first tier. This partial detailed verification provides sufficient accuracy to determine whether programming is complete, while avoiding the excessive time cost of detailed verification across all tiers, thus enabling faster program operations in multi-level cell formats.
Data Source
AI summary
A memory apparatus is provided and includes memory cells configured to retain a threshold voltage corresponding to data states. The memory cells are disposed in memory holes each connected to bit lines. Each of the bit lines is coupled to one of a plurality of sense amplifiers arranged in tiers. A control means is configured to program the memory cells in each of a plurality of program iterations of a program operation. The control means counts a failure quantity of a group of the memory cells having the threshold voltage below one of a plurality of verify voltages associated with one of the data states targeted for the memory cells in each of a plurality of verify iterations of a program operation. The count is a coarse count not separately counting the memory cells coupled with ones of the plurality of sense amplifiers of one or more of the tiers.