NAND Memory Coarse Read-Back Using Adaptive Read Voltages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND Flash memory devices face challenges in efficiently reading back coarse data during multi-pass program operations due to insufficient read window margins, leading to increased power loss handling duration and complexity.
Innovation Solution
A coarse data read-back scheme is introduced, utilizing adjusted read voltages and verify voltages to read back a portion of coarse-programmed data in response to a trigger event, such as power loss, ensuring sufficient read window margins and simplifying power loss handling processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If adjusted read voltages are applied to read back coarse data during multi-pass program operations, then read window margins are sufficient and power loss handling is simplified, but additional voltage adjustment circuitry and control logic are required
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the read voltage level based on the programming pass stage. During coarse programming passes, the read voltage is adjusted to a first level that provides adequate read window margin for intermediate levels. In the final programming pass, the read voltage is adjusted to a second level optimized for final levels. This voltage parameter adjustment ensures reliable data reading throughout the multi-pass process without requiring additional hardware circuitry beyond standard voltage control mechanisms.
Solution Approach 2:
The patent implements dynamics by making the read voltage adaptive and changeable based on the current programming pass. The system dynamically switches between different read voltage levels depending on whether intermediate or final levels are being read. This dynamic voltage adjustment allows the same hardware to serve multiple functions across different programming stages, avoiding the need for separate dedicated circuitry for each reading scenario.
2Loss of time
If coarse data is read back during multi-pass program operations, then power loss handling duration is reduced, but read operations may fail due to insufficient read window margins
Solution Approach 1:
The patent resolves this contradiction by changing the read voltage parameter according to the programming pass stage. When reading intermediate levels during coarse passes, a first read voltage level is applied that provides sufficient read window margin to ensure successful reading. When reading final levels in the last pass, a second read voltage level is used. This parameter adaptation enables timely read-back operations without sacrificing read reliability.
3Measurement precision
If different read voltages are applied for intermediate and final levels, then read accuracy is improved, but control logic complexity increases
Solution Approach 1:
The patent achieves high read accuracy through parameter changes in voltage levels while managing control logic complexity by tying voltage selection to the existing multi-pass programming structure. The control logic determines which read voltage to apply based on the current pass number and target level type (intermediate or final), leveraging information already available in the programming control flow rather than adding independent voltage selection logic.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
In certain aspects, a memory device includes an array of memory cells in columns and rows, word lines respectively coupled to rows of the memory cells, and a peripheral circuit coupled to the rows of memory cells through the word lines. Each memory cell is set to one of 2N final levels corresponding to a piece of N-bits data, where N is an integer greater than 2. The peripheral circuit is configured to program, in a first pass, a select row of the rows of the memory cells based on N data pages, such that each memory cell of the selected row is set to one of k intermediate levels, where k is an integer not greater than 2N. The peripheral circuit is also configured to read M data pages of the N data pages from the select row after the first pass, where M is an integer smaller than N.