NAND Memory Valley Voltage Estimation for Accurate Codeword Reads
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Solution Overview
Problem
The accuracy of data reading in NAND memory devices is affected by the variation of stored charges over time and temperature, leading to increased read errors and inability of existing error correction mechanisms to handle these changes effectively.
Innovation Solution
A memory device and system that utilize a peripheral circuit to obtain multiple read results at different voltages, apply a preset function model to predict a target valley voltage, and determine this voltage as the optimal read voltage for accurate data retrieval, thereby reducing the need for iterative error correction attempts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional read operations are used with fixed read voltages, then the device complexity is low, but the reading accuracy deteriorates due to charge variation over time and temperature
Solution Approach 1:
The patent applies preliminary action by pre-establishing a function model that describes the relationship between read voltage and charge retention characteristics. Before actual data reading, the system performs a voltage search procedure to determine the optimal read voltage based on this model, thereby proactively compensating for charge variations due to time and temperature effects, which improves reading accuracy without requiring complex real-time adjustment mechanisms during read operations.
Solution Approach 2:
The patent implements feedback through an iterative voltage search procedure that measures actual read results at different voltages and uses this information to refine the determination of the optimal read voltage. The system continuously adjusts the read voltage based on feedback from read operations, comparing results and converging on the voltage that maximizes reading accuracy, thus dynamically adapting to charge variations while maintaining manageable device complexity.
2Reliability
If iterative error correction attempts are performed to handle read errors, then the reliability of data retrieval improves, but the time consumption increases
Solution Approach 1:
The patent applies preliminary action by determining the optimal read voltage before performing data reading operations. By using the voltage search procedure to identify the best read voltage in advance, the system minimizes read errors at their source, thereby reducing the need for subsequent iterative error correction attempts and significantly decreasing the time required for reliable data retrieval.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a function model and voltage search procedure that mediates between the physical charge storage and the data reading process. This intermediary layer predicts and compensates for charge variations, providing accurate read voltage values that prevent errors before they occur, thus eliminating the need for time-consuming error correction iterations.
3Measurement precision
If the read voltage is adjusted dynamically based on charge variation, then the reading accuracy improves, but the operation complexity increases
Solution Approach 1:
The patent applies self-service by enabling the memory device to automatically determine and adjust its own optimal read voltage using internal measurements and the pre-established function model. The voltage search procedure is performed autonomously within the device, utilizing internal read operations and error detection capabilities to identify the best read voltage without requiring external control or complex external adjustment circuits, thereby improving reading accuracy while maintaining ease of operation.
Data Source
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AI summary
Examples of the present application disclose a memory device, an operation method thereof, a memory system, a memory controller, and a storage medium. The memory device includes: a memory cell array including a plurality of memory cells, a preset number of the memory cells forming a code word; and a peripheral circuit coupled with the memory cell array and configured to: obtain M first results corresponding to at least one code word at M target read voltages, wherein the first result includes a number of bits which represents the number of flipped bits in the at least one code word in two read results at a first read voltage and a second read voltage having a difference of less than a preset voltage from the first read voltage; obtain a predicted valley voltage according to the M first results and the M target read voltages in conjunction with a preset function model that represents a relationship between the first result and the target read voltage; and determine a target valley voltage based on the predicted valley voltage, wherein the target valley voltage is configured as a read voltage for a read operation on the at least one code word; and M is an integer greater than or equal to 1.