3D NAND Conductive Column Isolation for Leakage Prevention
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Solution Overview
Problem
In three-dimensional NAND memory devices, the high density and reduced distance between conductive and channel column structures lead to increased lengths, causing electric leakage or short circuits due to proximity issues.
Innovation Solution
A method involving the formation of a conductive column structure with a liner insulating layer as a shell to enhance isolation between the conductive and channel column structures, using materials like tungsten, copper, or polysilicon, and dielectric layers to reduce the risk of leakage by creating a skewed-face structure and ensuring the conductive column is higher than the channel column.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the distance between conductive column structure and channel column structure is reduced to increase density, then the memory device area is reduced, but electric leakage or short circuit occurs due to increased length and proximity
Solution Approach 1:
A liner insulating layer is introduced as an intermediary between the conductive column structure and channel column structure. This thin film layer acts as a mediator that provides electrical isolation while occupying minimal space, thereby maintaining device density while preventing leakage and short circuits.
Solution Approach 2:
The liner insulating layer is implemented as a thin film structure that conforms to the surface of the conductive column structure. This thin film provides effective electrical isolation without adding significant lateral dimension, enabling close spacing between columns while maintaining reliability.
2Productivity
If the length of conductive column structure and channel column structure is increased to support more word line layers, then the memory capacity is increased, but the risk of electric leakage and short circuit increases
Solution Approach 1:
The liner insulating layer serves as a continuous intermediary along the entire length of the conductive column structure, providing consistent electrical isolation from the channel column structure regardless of the vertical extent of the columns, thereby enabling high memory capacity without compromising reliability.
Solution Approach 2:
The isolation mechanism is shifted from a lateral dimension approach to a vertical dimension approach by applying the liner insulating layer as a coating on the conductive column structure, providing isolation along the length of the columns without increasing lateral spacing.
Data Source
AI summary
A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.