3D NAND Gate Contact Plug Layout for Higher Integration Density
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Solution Overview
Problem
Existing semiconductor devices face challenges in maximizing data storage capacity while minimizing the area required for contact plugs connected to gate electrodes, leading to inefficiencies in integration and space utilization.
Innovation Solution
The semiconductor device employs a stack structure with gate electrodes spaced apart and separated by regions, allowing contact plugs of varying lengths to be connected to different levels without additional etching steps, enabling flexible arrangement and maximizing the number of contact plugs without excess space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If contact plugs are arranged in a conventional uniform pattern, then the layout is simple to manufacture, but the area occupied by contact plugs increases and integration density decreases
Solution Approach 1:
The patent applies asymmetry by varying the lengths of contact plugs to match different gate electrode levels. Instead of using uniform-length contact plugs arranged in a regular pattern, the invention uses contact plugs with different lengths (first length for first gate electrode level, second length for second gate electrode level) to create an asymmetric layout that reduces the area occupied by contact plugs while maintaining manufacturing simplicity through the stack structure.
Solution Approach 2:
The patent transitions from a two-dimensional uniform arrangement to a three-dimensional asymmetric arrangement by varying contact plug lengths in the vertical dimension. This dimensional change allows contact plugs to reach different gate electrode levels (first and second levels) while reducing the horizontal footprint, thereby decreasing the area occupied by contact plugs and improving integration density.
2Productivity
If the number of contact plugs is increased to improve integration density, then the degree of integration improves, but the area required for contact plug arrangement increases
Solution Approach 1:
The patent utilizes the vertical dimension by creating contact plugs of different lengths that extend to different gate electrode levels (first level and second level). This allows multiple contact plugs to be arranged within a smaller horizontal area by stacking them vertically, thereby increasing integration density without proportionally increasing the area required for contact plug arrangement.
Solution Approach 2:
The patent implements nesting by placing contact plugs of different lengths within the same horizontal footprint. Shorter contact plugs are nested within the vertical space occupied by longer contact plugs, allowing multiple contact plugs to share the same horizontal area while reaching different gate electrode levels, thus increasing integration density without expanding the contact plug arrangement area.
3Adaptability or versatility
If contact plugs are made to reach different gate electrode levels, then connectivity to multiple gate electrodes is achieved, but additional etching steps are required
Solution Approach 1:
The patent applies segmentation by dividing the contact plug structure into different length segments corresponding to different gate electrode levels. The first contact plugs have a first length to reach the first gate electrode level, while the second contact plugs have a second length to reach the second gate electrode level. This segmentation allows connectivity to multiple gate electrodes without requiring complex additional etching steps, as the different lengths are achieved through the stack structure formation process.
Solution Approach 2:
The patent implements preliminary action by pre-forming the stack structure with gate electrodes at different levels before contact plug formation. The stack structure is prepared in advance with the first gate electrode at a first level and the second gate electrode at a second level, allowing contact plugs of different lengths to be formed in a single etching process that reaches these pre-positioned gate electrodes, thereby achieving multi-level connectivity without additional etching steps.
Data Source
AI summary
A semiconductor device includes: a conductive layer; a stack structure including gate electrodes spaced apart from each other and sequentially stacked in a first direction, in a first region and a second region, a first separation region and a second separation region penetrating through the stack structure, and extending in a second direction, perpendicular to the first direction, and spaced apart from each other in a third direction, perpendicular to the first direction and the second direction; channel structures respectively including a channel layer and penetrating through the stack structure in the first direction, in the first region; and contact plugs extending by different lengths by penetrating through at least one of the gate electrodes of the stack structure, electrically connected to each of the gate electrodes, and spaced apart from each other, in the second region.