3D NAND Contact Structure With Etch-Stop Landing for Staircase Isolation
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Solution Overview
Problem
In 3D NAND flash memory devices, the formation of contact holes through the staircase region poses challenges due to the risk of etching through the top gate layers, leading to potential leakage or shorts between word lines, and existing techniques struggle to isolate sacrificial layers effectively, affecting the integrity of the memory stack.
Innovation Solution
The use of a stair step isolation layer, deposited by atomic layer deposition, which is etch-selective to silicon nitride, and the formation of landing structures with etch stop structures, helps in preventing etching through the top gate layers and isolating sacrificial layers, ensuring proper contact hole formation and preventing leakage between word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact holes are etched through the staircase region to connect to gate layers, then electrical connections are established, but the risk of etching through the top gate layers increases, leading to potential leakage or shorts between word lines
Solution Approach 1:
The patent applies preliminary action by forming an etch stop structure (comprising a first etch stop layer and a second etch stop layer) at the target depth position before etching the contact holes. The first etch stop layer is formed at the bottom surface of the first gate layer, and the second etch stop layer is formed on the first etch stop layer. These pre-formed structures serve as depth references during the etching process, preventing the etch from penetrating through the top gate layers and causing shorts between word lines.
2Stability of the object's composition
If sacrificial layers are used to define stair steps, then the memory stack structure is formed, but effective isolation of sacrificial layers becomes difficult, affecting the integrity of the memory stack
Solution Approach 1:
The patent applies the intermediary principle by introducing a stair step isolation layer between adjacent sacrificial layers in the staircase region. This isolation layer physically separates the sacrificial layers, preventing unwanted interactions and ensuring proper isolation during the formation process. The stair step isolation layer acts as a mediator that maintains the integrity of the memory stack while allowing the sacrificial layers to be properly isolated from each other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the operation window for contact hole formation, prevents leakage, and ensures reliable connections between gate layers, thereby improving the overall performance and reliability of the 3D NAND flash memory devices.
Implementation Method 1
The use of a stair step isolation layer, deposited by atomic layer deposition, which is etch-selective to silicon nitride
Data Source
AI summary
Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers, a landing structure and a contact structure. The gate layers and the insulating layers are stacked alternatingly, and form stair steps in a staircase region. The landing structure is disposed on a first gate layer of a first stair step of the stair steps in the staircase region. The landing structure includes an upper structure and an isolation stack between the upper structure and the first gate layer. The upper structure is etch-selective to a contact isolation layer that covers the staircase region. The contact structure extends through the contact isolation layer and the landing structure and is connected with the first gate layer of the first stair step.