3D NAND Contact Layout With Stepped Gate Lines for Smaller Chips
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Solution Overview
Problem
Current NAND-type flash memory devices face challenges in reducing chip size and operational load during read and write operations due to inefficient contact unit structures, which affect data storage capacity and performance.
Innovation Solution
The semiconductor memory device employs a three-dimensional memory cell array with conductive layers forming selection gate lines, word lines, and drain-side selection gate lines, featuring stepwise structures in the X and Y directions for contact units, allowing for reduced chip size and decreased operational load by enabling selection of gate lines per finger and minimizing contact areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact units have large contact areas to ensure sufficient electrical connection, then electrical reliability is improved, but chip size increases and manufacturing precision becomes more difficult
Solution Approach 1:
The contact units are divided into multiple contact holes arranged in a matrix pattern, with each contact hole providing a portion of the total electrical connection. This segmentation allows the electrical load to be distributed across multiple smaller contact areas rather than requiring one large contact area, thus maintaining reliability while reducing overall chip size.
Solution Approach 2:
The patent transitions from planar contact arrangements to three-dimensional stacked contact holes at angled orientations. By arranging contact holes in multiple layers and angles (e.g., 45-degree angles in different directions), the patent achieves sufficient electrical connection capacity without increasing the planar footprint, effectively utilizing the vertical dimension to reduce chip area.
2Quantity of substance
If more contact units are added to increase data storage capacity, then memory capacity is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The contact units are designed with a standardized matrix arrangement and uniform structural characteristics that serve multiple functions: electrical connection, address decoding, and data storage. This universal design allows the same contact unit structure to be replicated across the array, increasing storage capacity without proportionally increasing device complexity, as each unit follows the same pattern.
Solution Approach 2:
The patent uses three-dimensionally stacked contact holes arranged in a matrix pattern, utilizing vertical stacking to increase the number of contact units without proportionally increasing planar area. This dimensional approach allows higher storage density while maintaining manageable structural complexity through regular patterning.
3Ease of manufacture
If conventional contact unit structures are used, then manufacturing process is simpler, but operational load during read and write operations increases
Solution Approach 1:
The contact units are segmented into multiple contact holes with distributed electrical connections. This segmentation reduces the operational load on each individual contact by distributing the current and signal traffic across multiple pathways, thereby reducing resistance and heating effects during read and write operations while maintaining manufacturing simplicity through standardized patterns.
4Quantity of substance
If chip size is reduced to increase storage density, then storage capacity per unit area is improved, but contact unit structural integrity and electrical connection quality deteriorate
Solution Approach 1:
The patent employs three-dimensionally stacked contact holes arranged in a matrix pattern with angled orientations. This dimensional approach increases storage density by utilizing vertical space rather than only planar area, while the angled stacking provides mechanical support and maintains electrical connection quality through optimized current pathways that reduce resistance and improve signal integrity.
Data Source
AI summary
A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.