3D NAND Memory Controller ECC Reliability Check
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Solution Overview
Problem
As the capacity and integration of 3D NAND flash memory devices increase, they face reliability issues due to data destruction problems not previously encountered, affecting the storage device's reliability.
Innovation Solution
A storage device with a non-volatile memory and a memory controller that performs a reliability check using error correction code (ECC) data, involving a first read operation for error correction and a second read operation to count errors, allowing for a reclaim operation to maintain data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacity and integration of 3D NAND flash memory devices are increased, then the storage capacity is improved, but data destruction problems occur and reliability deteriorates
Solution Approach 1:
The patent performs a first read operation followed by error correction decoding before performing a second read operation to count errors. This preliminary error correction action allows the system to identify and correct data destruction issues before they propagate, enabling reliability checking in high-capacity 3D NAND flash memory devices without sacrificing storage capacity
2Reliability
If a reliability check is performed using traditional methods, then data reliability is verified, but the time required for the check increases
Solution Approach 1:
The patent extracts and utilizes existing ECC data from the first read operation to perform reliability checking. By taking out and reusing the ECC data that is already read during normal operations, the system can count errors in a second read operation without requiring additional time-consuming external verification processes, thus maintaining data reliability while minimizing check time
Data Source
AI summary
A storage device for performing a reliability check by using error correction code (ECC) data is provided. The storage device includes a memory controller configured to detect the number of errors of second read data read out by a second read operation, based on ECC data of first read data read by a first read operation of a memory device. The memory controller includes a memory check circuit that includes a counter configured to count states of memory cells, a comparator configured to compare respective count numbers of the states with one another, and a register configured to store the number of errors based on a result of the comparison.