NAND Memory Controller LLR Adjustment for Threshold Voltage Drift
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Solution Overview
Problem
The increasing error rates in data decoded from NAND flash memory due to threshold voltage shifts in non-volatile memory cells, caused by factors like read and program disturb, charge leakage, and program/erase cycles, hinder the accuracy of log likelihood ratio (LLR) values used in LDPC decoding, making it difficult to obtain error-free data.
Innovation Solution
A method and device that provide adjusted LLR values for LDPC decoders by comparing distributions of charge states over time, using translation circuitry and a distribution processor to determine threshold voltage shifts, and generating corrected LLR values to compensate for these shifts, thereby improving decoding accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple reads are performed at varying threshold voltages to obtain soft information for LDPC decoding, then decoding accuracy is improved, but threshold voltage shifts due to read disturb, charge leakage, and program/erase cycles cause error rates to increase over time
Solution Approach 1:
The patent performs preliminary characterization of threshold voltage shifts by comparing charge state distributions at different times (initial vs. aged states). This preliminary analysis establishes correction factors that are stored and applied during subsequent read operations, allowing the system to preemptively compensate for threshold voltage drift before it causes decoding failures.
Solution Approach 2:
The patent dynamically adjusts the log-likelihood ratio (LLR) values based on detected threshold voltage shifts. By comparing charge state distributions at different times and calculating the shift magnitude, the system modifies the LLR parameters fed to the LDPC decoder, thereby adapting the decoding process to current memory cell conditions and maintaining high decoding accuracy despite aging effects.
2Reliability
If charge programming variations are allowed to follow statistical distributions rather than discrete values, then memory cell state representation becomes more realistic, but error correction becomes more difficult due to overlapping charge distributions
Solution Approach 1:
The patent implements a feedback mechanism where charge state distributions are continuously monitored and compared between initial and aged states. The detected shifts in distribution characteristics feed back into the LLR adjustment process, allowing the system to adaptively compensate for the overlapping distributions caused by programming variations and aging, thereby maintaining error correction effectiveness.
Solution Approach 2:
The patent transitions from static threshold voltage assumptions to dynamic adaptation by continuously characterizing charge state distributions. The system dynamically calculates threshold voltage shifts based on current memory cell states and adjusts decoding parameters in real-time, enabling the error correction mechanism to respond to changing distribution overlaps caused by aging and programming disturbances.
3Productivity
If threshold voltage shifts are allowed to accumulate over time due to read/program disturb and charge leakage, then memory device operation continues without intervention, but soft LDPC decoding becomes impossible to obtain error-free data
Solution Approach 1:
The patent employs continuous feedback monitoring of charge state distributions to detect threshold voltage shifts that accumulate during normal operation. By comparing distributions at different times and detecting drift patterns, the system identifies when threshold shifts are approaching levels that would cause decoding failures, allowing for timely compensation through LLR adjustment.
Solution Approach 2:
The patent enables the memory system to self-correct for threshold voltage shifts without external intervention. The automatic characterization of charge state distributions, calculation of shift amounts, and adjustment of LLR values create a self-service mechanism that maintains decoding reliability throughout the memory device's operational life, even as threshold voltages drift due to aging and usage.
Data Source
AI summary
There is provided a method of providing adjusted LLR values of a plurality of bits in a codeword to an LDPC decoder, the plurality of bits representing a plurality of charge states of a plurality of memory cells of a non-volatile memory. The method comprises storing in a non-volatile memory controller associated with the non-volatile memory LLR values of the plurality of bits. The controller then determines a plurality of levels of the charge states represented by the plurality of bits. The controller then generates, by a distribution processor, distributions of a population of the plurality of bits in the codeword at each of the plurality of levels at a first and a second time after the first time. The controller then generates the adjusted LLR values based on a comparison between the first and second distributions, and then decodes the codeword according to the adjusted LLR values.