NAND Flash Controller Margin Measurement
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Solution Overview
Problem
Measuring voltage and timing margins in compact data storage devices like SSDs and SD cards is challenging due to their compact nature, making it inconvenient and time-consuming, and can lead to signal integrity issues and read/write failures.
Innovation Solution
A storage device with a controller featuring a differential receiver and a delay locked loop circuit that varies the delay of a data strobe signal across a data window to determine timing margins and applies a reference voltage to measure voltage margins, allowing for automated and precise margin determination during read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If physical probes are connected to test points on the interface to measure timing and voltage margins, then measurement can be performed, but the approach is inconvenient, time-consuming, and causes signal integrity issues
Solution Approach 1:
The storage device performs self-diagnosis by incorporating margin measurement functionality directly into the controller. The controller automatically varies delay of data strobe signals and adjusts reference voltages to determine timing and voltage margins without requiring external probes or manual intervention, making the device self-testing and eliminating the need for lab equipment
Solution Approach 2:
The patent introduces an intermediary testing mechanism where the controller uses internal delay locked loop circuits and reference voltage generation to create test signals that pass through the memory interface. This intermediary approach allows margin measurement through normal interface operations rather than direct probe connections, maintaining signal integrity while enabling automated testing
2Measurement precision
If physical probes are connected to test points on the interface to measure timing and voltage margins, then measurement can be performed, but the presence of test points causes signal integrity issues and read/write failures
Solution Approach 1:
The patent introduces an intermediary testing mechanism where the controller uses internal delay locked loop circuits and reference voltage generation to create test signals that pass through the memory interface. This intermediary approach allows margin measurement through normal interface operations rather than direct probe connections, maintaining signal integrity while enabling automated testing
Solution Approach 2:
The patent replaces the mechanical probe connection system with an electronic self-testing system. Instead of physically connecting external probes to test points, the controller electronically generates test signals and measures margins through software-controlled operations, eliminating the physical intrusion that causes signal integrity issues
3Productivity
If automated margin measurement is implemented within the controller, then measurement convenience and speed improve, but device complexity increases
Solution Approach 1:
The controller is designed with multi-functionality, where the delay locked loop circuit and reference voltage generation capabilities serve dual purposes: they are used for normal high-speed data operations and simultaneously for automated margin measurement. This universal design allows the same hardware components to perform both data processing and self-diagnosis functions
Solution Approach 2:
The patent merges the margin measurement functionality with the existing controller architecture by integrating delay locked loop circuits and reference voltage generation into the controller's data path. This consolidation combines testing functions with operational functions, reducing the need for separate dedicated testing hardware and minimizing additional complexity
Data Source
AI summary
A storage device comprises a controller, such as an ASIC controller, and one or more NAND flash memory devices. The controller comprises a differential receiver and a delay locked loop circuit. During read and write operations, the controller is configured to vary a delay of a data strobe signal by an interval across a width of a data window using the delay locked loop circuit, and to compare a write pattern to a read pattern for each delayed interval to determine the timing margins of the storage device. During read and write operations, the controller is further configured to apply a reference voltage to a host interface or a memory interface, increment and decrement the reference voltage by a set value, and compare a write pattern to a read pattern for each varied reference voltage value to determine the voltage margins of the storage device.