NAND Flash Controller Electrical Mirroring for Signal Integrity

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Solution Overview

Problem

The multi-load NAND interface topology in SSDs faces challenges with signal integrity due to long trace lengths between NAND devices, leading to performance degradation, and existing electrical mirroring techniques have high error tolerance and failure rates, making them unreliable.

Innovation Solution

Implementing a flexible and robust electrical mirroring technique where the storage controller determines whether mirroring is enabled for each NAND device, using firmware to set register bits and reverse data pin orders, allowing for shorter trace lengths and improved PCB layout quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a multi-load PCB topology is used to integrate more NAND flash devices, then storage capacity increases, but signal integrity degrades due to long trace lengths

Engineering Contradiction:
Improvestorage capacityVSAvoidsignal integrity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies asymmetry by implementing electrical mirroring that reverses the pin order for flipped NAND devices. Instead of treating all devices symmetrically, the controller dynamically adjusts data bit ordering based on device orientation, creating an asymmetric solution that accommodates both regular and flipped device placements while maintaining signal integrity through optimized trace routing.

Inventive Principle:
Principle #4Asymmetry

2Length of stationary object

If NAND devices are placed in mirrored configuration to improve PCB layout, then trace lengths are reduced, but existing electrical mirroring techniques have high error rates

Engineering Contradiction:
Improvetrace lengthVSAvoidelectrical mirroring reliability
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The patent changes the parameter of data bit ordering dynamically based on device detection. The controller detects whether a NAND device is flipped and accordingly reverses or maintains the original data bit order, transforming a static electrical mirroring approach into a dynamic parameter adjustment that eliminates error tolerance issues while achieving short trace lengths.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The implementation incorporates feedback mechanisms where the controller detects the physical state of NAND devices and adjusts data bit ordering accordingly. This feedback loop ensures that the electrical mirroring configuration matches the actual device placement, eliminating the high error rates associated with static mirroring approaches.

Inventive Principle:
Principle #23Feedback

3Reliability

If electrical mirroring is implemented to shorten traces, then signal integrity improves, but device complexity increases due to pin map management

Engineering Contradiction:
Improvesignal integrityVSAvoidpin map management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system implements self-service by automatically detecting device orientation and configuring the appropriate pin maps without manual intervention. The controller autonomously determines whether to apply reversed or regular pin maps based on detected device states, eliminating the need for complex manual pin map management while maintaining signal integrity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11726695B2Electrical mirroring by NAND flash controller
Publication Date: 2023.08.15 INNOGRIT TECH CO LTD
  • US11726695B2 patent drawing
  • US11726695B2 patent drawing
  • US11726695B2 patent drawing

AI summary

Systems, apparatus and methods are provided for electrical mirroring implemented by a storage controller in a non-volatile storage system. In one embodiment, a non-volatile storage system may comprise a plurality of non-volatile storage devices and a storage controller. The storage controller may be configured to perform an electrical mirroring configuration process comprising: determining a system topology of the non-volatile storage system and which targets are in mirrored non-volatile storage devices and setting respective register bits in the storage controller for all targets in all mirrored non-volatile storage devices of the plurality of non-volatile storage devices.