NAND Controller Dynamic Read Command Delay for Parallel Execution

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Solution Overview

Problem

Current NAND memory devices often fail to maximize the probability of parallel execution of read commands across different portions of a single die, leading to suboptimal read throughput due to the requirement of multiple commands targeting the same die simultaneously, which is rare in certain workloads.

Innovation Solution

Introducing a delay mechanism for issuing read commands to increase the likelihood of multi-plane read execution, where if no other eligible read commands are present, the controller delays the command issuance until a compatible second read command is received or the delay period expires, allowing for simultaneous execution of multiple read commands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If read commands are issued immediately without delay, then single-command latency is minimized, but the probability of parallel execution across different portions of the die is reduced

Engineering Contradiction:
Improvesingle-command latencyVSAvoidread throughput
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The controller delays issuing the first read command for a predetermined time period before actual execution. This preliminary delay allows time for a second read command to be received, enabling both commands to be executed in parallel across different portions of the die, thereby increasing read throughput while accepting a slight increase in single-command latency

Inventive Principle:
Principle #10Preliminary action

2Productivity

If multiple read commands are executed in parallel, then read throughput is increased, but system complexity increases due to command queue management and timing coordination

Engineering Contradiction:
Improveread throughputVSAvoidcommand coordination complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The die is divided into different portions (e.g., planes or command queues) that can independently execute read commands. By segmenting the memory structure and associating different command queues with different portions, the system enables parallel execution while maintaining manageable complexity through modular organization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The controller dynamically determines whether to delay or immediately execute read commands based on real-time conditions such as whether a second command is received within the delay period. This dynamic adaptation allows the system to optimize for parallel execution when possible while falling back to immediate execution when not, balancing throughput gains against latency costs

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11621042B2Dynamic delay of NAND read commands
Publication Date: 2023.04.04 MICRON TECHNOLOGY INC
  • US11621042B2 patent drawing
  • US11621042B2 patent drawing
  • US11621042B2 patent drawing

AI summary

Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which increase read throughput by introducing a delay prior to issuing a command to increase the chances that read commands can be executed in parallel. Upon receipt of a read command, if there are no other read commands in the command queue for a given portion (e.g., plane or plane group) of the die, the controller can delay issuing the read command for a delay period using a timer. If, during the delay period, an eligible read command is received, the delayed command and the newly received command are both issued in parallel using a multi-plane read. If no eligible read command is received during the delay period, the read command is issued after the delay period expires.