NAND Flash Memory Controller Read Latency Reduction
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Solution Overview
Problem
NAND flash memory systems face significant read latency issues due to the inability to perform read and write operations simultaneously, which hinders performance in real-time applications and is exacerbated by the limitations of existing memory architectures like NOR flash.
Innovation Solution
An additional set of commands and/or registers is introduced to create a 'virtual' port in the memory controller, allowing for read access during write or erase operations by prioritizing read requests or suspending write operations, enabling simultaneous read and write capabilities even with a single NAND chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If read operations are performed in NAND flash memory during write operations, then read latency is reduced, but the memory architecture becomes more complex
Solution Approach 1:
The patent divides the memory system into multiple independent NAND chips or partitions, allowing the memory controller to manage read and write operations on different segments simultaneously. This segmentation enables parallel access without requiring complex internal restructuring of single chip operations.
Solution Approach 2:
The memory controller acts as an intermediary that manages multiple command queues and coordinates operations between the host and NAND memory chips. It introduces additional command registers and state machines to mediate between read and write requests, enabling simultaneous operations without direct conflict at the chip level.
2Productivity
If simultaneous read and write operations are enabled, then system productivity improves, but the reliability of write operation completion decreases
Solution Approach 1:
The patent implements a suspend capability that allows write operations to be temporarily paused before completion when high-priority read operations are needed. The write state information is preserved, and the operation can be resumed later, ensuring eventual completion while enabling urgent reads in between.
Solution Approach 2:
The memory controller implements feedback mechanisms through command registers and status flags that track the state of ongoing write operations. This feedback system allows the controller to make informed decisions about suspending or continuing write operations based on current system needs, ensuring reliable coordination of simultaneous operations.
Data Source
AI summary
Systems, apparatuses and methods for controlling access operations in a memory device that may include a memory controller(s) and memory. Commands, registers and/or other mechanisms may be defined to be supported by the memory device, where such commands, registers, and/or other mechanisms facilitate the control of read and write/erase operations to allow these operations to be performed simultaneously. Thus, a write and/or erase operation may be initiated on a first memory, a read operation initiated by a set of commands on a second memory, wherein the read and write/erase operations are performed substantially at the same time.