NAND Controller Multi-Plane Read Pairing
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Solution Overview
Problem
Existing storage devices face performance degradation due to the time-consuming process of address conversion in nonvolatile semiconductor memory, particularly when accessing multiple planes in NAND memory, which affects read and write operations.
Innovation Solution
A storage device and method that classify read requests into first and second read requests, pair them to generate multi-plane read requests, and output these to nonvolatile semiconductor memory, allowing parallel data reading across multiple planes, thereby improving throughput and mitigating performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If address conversion is performed sequentially for each read request in nonvolatile semiconductor memory, then address accuracy is maintained, but read speed deteriorates
Solution Approach 1:
The patent performs address conversion in advance by pre-translating logical addresses to physical addresses and storing the converted address information in a buffer memory before actual data read operations occur. This preliminary address conversion eliminates the need for time-consuming address translation during critical read operations, thereby improving read speed while maintaining address accuracy.
Solution Approach 2:
The patent divides the address conversion process into separate stages: logical address to physical address conversion is performed independently and stored in buffer memory, while the actual data read operation proceeds separately. This segmentation allows address conversion and data retrieval to be decoupled, enabling parallel processing and reducing overall operation time.
2Productivity
If multiple read requests are processed sequentially across different planes, then address conversion accuracy is maintained, but throughput deteriorates
Solution Approach 1:
The patent merges multiple read requests targeting different planes into a single coordinated operation by consolidating their address conversion results in the buffer memory. This allows the storage device to execute multiple plane reads in parallel rather than sequentially, significantly improving throughput while maintaining the integrity of individual address conversions through the buffer storage mechanism.
Solution Approach 2:
The patent ensures continuous data retrieval operations by maintaining a buffer of pre-converted address information that enables uninterrupted parallel reads across multiple planes. The buffer memory continuously supplies physical address information to multiple read operations simultaneously, eliminating idle time between sequential operations and maintaining continuous productive action.
Data Source
AI summary
A storage device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a first region and a second region. The controller classifies a plurality of read requests for reading data from the nonvolatile semiconductor memory into first read requests for reading data from the first region and second read requests for reading data from the second region, pairs one of the first read requests with one of the second read requests to generate a third read request, and outputs the third read request to the nonvolatile semiconductor memory.