NAND Flash Controller Selective ECC for Copy Speed
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Solution Overview
Problem
NAND flash memory devices face inefficiencies in data copying due to frequent error correction processes, which increase the load on the controller and prolong the time required for data overwrite operations, as they cannot directly overwrite data without first copying it to a new block and performing error detection and correction.
Innovation Solution
A storage device with a controller that reads data using upper and lower limit voltages to determine threshold voltages of memory cells, allowing for direct copying without ECC circuit intervention if the number of error cells is within a specified limit, and performing error correction using the ECC circuit when the error count exceeds this limit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed using the ECC circuit for all data copy operations, then data reliability is improved, but the processing time and controller load increase significantly
Solution Approach 1:
The patent applies partial error correction by first performing a quick error check on read data, and only invoking the ECC circuit when errors are detected. This partial approach avoids the excessive time consumption of full ECC processing for all data while maintaining reliability when needed.
Solution Approach 2:
The patent replaces the mechanical ECC circuit error correction process with a simpler software-based error checking mechanism for initial validation. This substitution reduces the heavy processing load on the controller while maintaining data integrity through selective ECC usage.
2Reliability
If error correction is performed using the ECC circuit for all data copy operations, then data reliability is improved, but the controller load increases
Solution Approach 1:
The patent implements partial error correction by performing a lightweight error check first and only engaging the ECC circuit when necessary. This reduces the overall controller load while maintaining data reliability through targeted correction of actual errors.
Solution Approach 2:
The patent substitutes the complex ECC circuit mechanism with a simpler error checking approach for initial data validation. This reduces controller complexity and processing load while preserving data integrity by using ECC only when errors are detected.
3Reliability
If data is copied to a new block for overwriting in NAND flash memory, then data integrity is maintained, but the number of operations and time required increase
Solution Approach 1:
The patent performs preliminary error checking on read data before initiating the copy operation. This preliminary action identifies errors early, allowing for efficient error correction and enabling faster data overwrite operations by avoiding unnecessary processing steps.
Solution Approach 2:
The patent replaces the traditional mechanical copy-verify-correct sequence with an optimized flow where error checking is integrated into the read operation. This substitution streamlines the data overwrite process while maintaining integrity through selective ECC correction.
Data Source
AI summary
According to one embodiment, a storage device includes a nonvolatile memory, a controller configured to copy data stored in a first page in a first block to a second page in a second block, and an ECC circuit. The controller reads data from a part of the first page by using an upper limit voltage and lower limit voltage, performs a direct copy operation in the nonvolatile memory without via the ECC circuit if the number of error cells having threshold voltages higher than the lower limit voltage and lower than or equal to the upper limit voltage is less than or equal to a specified value, and performs error correction by using the ECC circuit if the number of error cells exceeds the specified value.