NAND Flash Controller Wear Distribution via Threshold Voltage Adjustment

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Solution Overview

Problem

NAND flash memory cells experience degradation and program disturbance due to repeated high threshold voltage applications and significant differences in threshold voltages between adjacent memory cells, leading to reduced lifespan and increased error rates.

Innovation Solution

A controller for NAND flash memory that includes an encoder and ECC shifter to convert data patterns with high threshold voltage differences into patterns with smaller differences, and dynamically shifts the ECC and code book areas within a page based on write and erase operations to distribute wear evenly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If high threshold voltage is repeatedly applied to memory cells to store multilevel data, then data storage capacity is improved, but memory cell lifespan is reduced due to tunnel oxide film degradation

Engineering Contradiction:
Improvedata storage capacityVSAvoidmemory cell lifespan
Core Design Contradiction:
Quantity of substanceVSDuration of action of stationary object

Solution Approach 1:

The controller dynamically adjusts threshold voltage levels based on wear information stored in memory cells. By changing the parameter of threshold voltage application from fixed high voltage to variable voltage levels, the system maintains data storage capacity while reducing oxidative stress on tunnel oxide films, thereby extending cell lifespan.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system implements feedback by reading wear information from memory cells and using this information to control subsequent write operations. The controller modifies threshold voltage applications based on real-time wear status, preventing excessive voltage stress on degraded cells and balancing overall wear distribution across the memory array.

Inventive Principle:
Principle #23Feedback

2Quantity of substance

If great differences in threshold voltage are applied to adjacent memory cells to encode data, then data encoding capability is improved, but program disturbance occurs due to threshold voltage variation

Engineering Contradiction:
Improvedata encoding capabilityVSAvoidprogram disturbance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The controller modifies threshold voltage parameters dynamically based on the specific memory cell locations and their wear states. By adjusting threshold voltage levels individually for different cells rather than applying uniform high differences, the system maintains data encoding capability while minimizing threshold voltage variations between adjacent cells, thereby reducing program disturbance.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system applies different threshold voltage characteristics to different memory cells based on their individual wear information and positions in the array. This localized approach allows optimal data encoding for each cell while preventing excessive threshold voltage differences between adjacent cells, thus reducing program disturbance effects.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9792053B2Controller for nonvolatile semiconductor memory
Publication Date: 2017.10.17 KIOXIA CORP
  • US9792053B2 patent drawing
  • US9792053B2 patent drawing
  • US9792053B2 patent drawing

AI summary

According to one embodiment, a controller for a nonvolatile semiconductor memory that stores data expressed using n levels (n is a natural number not less than 3) page by page includes an extraction unit and a conversion unit. The extraction unit extracts a second data stream shorter than a first data stream from the first data stream that includes a plurality of data written to the nonvolatile semiconductor memory. The conversion unit converts the second data stream into a third data stream longer than the second data stream, when a difference between threshold voltages of the nonvolatile semiconductor memory corresponding to adjacent two data included in the second data stream is a first level difference. The third data stream has a second level difference smaller than the first level difference.