NAND Flash Controller Wear Distribution via Block Disassembly

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Solution Overview

Problem

In NAND flash memory systems, wear in tunnel oxide films due to repetitive programming and erasing operations leads to failed operations, resulting in unusable blocks and reduced storage capacity and performance over time.

Innovation Solution

A memory system with a controller circuit that manages logical blocks by monitoring erasing and programming time lengths of physical blocks, disassembling logical blocks when blocks with different wear levels are mixed, and reassembling them with blocks of similar wear characteristics to distribute wear evenly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If erase operations are performed on physical blocks in NAND flash memory, then storage capacity is utilized, but wear in tunnel oxide films increases leading to failed operations and reduced lifespan

Engineering Contradiction:
Improvestorage utilizationVSAvoidoperation success rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by monitoring and identifying physical blocks with different wear levels (good blocks with shorter erase times vs. worn blocks with longer erase times) and treating them differently through selective disassembly and reassembly operations, rather than uniformly treating all blocks

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent performs preliminary action by monitoring erase time lengths before blocks fail, identifying worn blocks in advance, and proactively disassembling logical blocks containing mixed wear-level blocks before actual failures occur, thereby preventing future operation failures

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If physical blocks with different wear levels are grouped in the same logical block, then erase operations can be performed, but wear distribution becomes uneven leading to premature failure of the logical block

Engineering Contradiction:
Improveerase operation capabilityVSAvoidlogical block lifespan
Core Design Contradiction:
Ease of operationVSDuration of action of stationary object

Solution Approach 1:

The patent segments logical blocks into smaller units and reassembles them based on wear characteristics, separating blocks with different wear levels into different logical blocks to ensure uniform wear distribution and extend overall system lifespan

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the composition parameter of logical blocks by dynamically selecting which physical blocks to group together based on their wear levels (erase time lengths), creating logical blocks with homogeneous wear characteristics to optimize performance and lifespan

Inventive Principle:
Principle #35Parameter changes

3Reliability

If worn physical blocks are treated as bad blocks, then failed operations are prevented, but total physical capacity is reduced and SSD lifespan is shortened

Engineering Contradiction:
Improveoperation reliabilityVSAvoidavailable storage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent recovers worn physical blocks by disassembling logical blocks containing mixed wear-level blocks and reassembling them into new logical blocks with uniform wear characteristics, thereby recovering capacity that would otherwise be lost and extending SSD lifespan

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS10366771B2Controller, memory system, and block management method for NAND flash memory using the same
Publication Date: 2019.07.30 KIOXIA CORP
  • US10366771B2 patent drawing
  • US10366771B2 patent drawing
  • US10366771B2 patent drawing

AI summary

Aspects of the present disclosure include a memory system monitors at least one of an erasing time length and a programming time length of each of physical blocks included in a first logical block among a plurality of logical blocks. The memory system disassembles the first logical block among the plurality of logical blocks when both of a first physical block and a second physical block exist in the first logical block, the first physical block having an erasing time length or a programming time length falling within a first range, and the second physical block having an erasing time length or a programming time length falling outside the first range.