NAND Flash Copy-Back Error Detection via Dual Voltage Read
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional NAND flash memory devices rely heavily on memory controllers for error detection and correction during power loss events, leading to inefficiencies and increased latency due to off-die operations, which are unsuitable for use in power loss management.
Innovation Solution
A copy-back module within the NAND die performs internal error detection by reading data at two different voltages within a read window, allowing for minimal or no intervention from the memory controller, and invokes error correction when necessary, ensuring data integrity without relying solely on external resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional NAND flash memory devices rely on memory controllers for error detection and correction during power loss events, then error handling capability is provided, but latency increases and efficiency decreases due to off-die operations
Solution Approach 1:
The patent implements self-service by enabling the NAND die to perform error detection and correction autonomously through on-die ECC circuitry. The system reads data at multiple voltage levels, performs error correction internally using embedded parity bits and syndrome decoding, and writes corrected data back without requiring memory controller intervention. This self-contained approach eliminates off-die communication overhead and reduces latency while maintaining reliability.
Solution Approach 2:
The patent segments the error handling process into distinct on-die functional blocks: voltage level switching circuitry, syndrome calculation units, parity bit extraction modules, and data reconstruction logic. These segmented functional units operate independently within the die, allowing parallel processing of error detection and correction tasks, thereby improving efficiency and reducing overall operation time.
2Reliability
If memory controllers are used for error detection and correction, then comprehensive error handling is achieved, but device complexity and external resource dependency increase
Solution Approach 1:
The system achieves self-service by integrating complete error detection and correction functionality within the NAND die. Embedded ECC circuitry calculates syndromes, detects errors using parity bits, and corrects data internally without external controller assistance. This reduces dependency on external resources while maintaining comprehensive error handling capability.
Solution Approach 2:
The patent merges error detection and correction functions directly into the NAND flash memory die, combining storage and error handling capabilities in a single integrated unit. The ECC circuitry, voltage switching logic, and data processing units are merged into the die structure, eliminating the need for separate external error handling resources and reducing overall system complexity.
3Measurement precision
If on-die error detection is implemented by reading data at two different voltages, then error detection precision improves, but operation time increases
Solution Approach 1:
The patent applies parameter changes by dynamically switching read voltage levels based on detected error conditions. The circuitry reads data at a first voltage level, detects errors through syndrome calculation, and if errors are found, re-reads at a different voltage level for correction. This conditional parameter switching achieves high detection precision while minimizing unnecessary operation time by only performing multiple reads when errors are actually present.
Solution Approach 2:
The system implements feedback by using syndrome calculation results to control subsequent read operations. The first read operation provides feedback to the error detection logic, which then determines whether a second read at a different voltage is necessary. This feedback-driven approach ensures high error detection precision while optimizing operation time by avoiding redundant reads when no errors are present.
Data Source
AI summary
Devices and techniques for performing copy-back operations in a memory device are disclosed herein. A trigger to perform a copy-back operation in relation to a section of data stored on the memory device can be detected. Circuitry of the memory device can then read the section of data at two voltage levels within a read window to obtain a first set of bits and a second set of bits respectively. The first and second sets of bits—which should be the same under normal circumstances—are compared to determine whether a difference between the sets of bits is beyond a threshold. If the difference is beyond a threshold, error correction is invoked prior to completion of the copy-back operation.