NAND IO Interface for SLC-to-PLC Copyback Cycle Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing NAND memory systems face performance limitations and complexity due to the high number of command-address-data cycles required for copyback program operations from SLC to PLC blocks, particularly in multi-level cell devices, which complicates system hardware and firmware management.
Innovation Solution
An enhanced IO interface utilizing two set-feature latches to store SLC start page and block addresses, enabling an enhanced mode that reduces the number of command-address-data cycles from 86 to 25 by internally pre-reading and transferring data to static page buffers before switching to PLC mode for program operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the existing interface is used for copyback program operations from SLC to PLC blocks, then data can be transferred between block types, but the number of command-address-data cycles increases significantly to 86 cycles, limiting system performance
Solution Approach 1:
The patent applies preliminary action by pre-reading SLC block data into internal buffers before the actual program operation is needed. The controller reads the SLC block data in advance and stores it in internal buffers, so when the program operation is triggered, the data is already ready for immediate transfer to PLC blocks, eliminating the need for sequential read-then-program operations and reducing cycles from 86 to 25.
Solution Approach 2:
The patent introduces internal buffers as intermediaries between the SLC block storage and PLC block programming operations. These buffers act as a mediator that decouples the read and program operations, allowing the controller to read SLC data into buffers first, then transfer to PLC blocks without requiring sequential command-address-data cycles for each operation, thus reducing the total cycle count.
2Productivity
If the existing interface manages the copyback operation sequence, then data transfer can be performed, but significant complexity is added to system hardware and firmware management
Solution Approach 1:
The patent applies self-service by enabling the memory controller to automatically manage the copyback operation sequence without requiring complex external control. The controller internally reads SLC block data into buffers, determines when PLC block programming is needed, and executes the transfer operations autonomously, simplifying the hardware/firmware management interface while maintaining data transfer capability.
Solution Approach 2:
The patent merges the read and program operations into a unified copyback process managed by the controller. Instead of treating read and program as separate sequential operations requiring complex coordination, the patent combines them into a single streamlined process where SLC data is read into internal buffers and then directly programmed to PLC blocks, reducing the management complexity of the interface.
3Reliability
If all five-page data is internally moved from SLC block to PLC block, then complete data transfer is achieved, but the operation requires 15 command-address sequences which decode to 86 cycles
Solution Approach 1:
The patent applies preliminary action by pre-reading all five pages of SLC block data into internal buffers before the program operation is triggered. This allows the complete data set to be ready for immediate transfer to PLC blocks in a single operation, ensuring data transfer completeness while reducing the operation from 15 command-address sequences (86 cycles) to just 25 cycles.
Data Source
AI summary
Methods and apparatus for Enhanced IO Interface for PLC program and program-suspend-resume operations. A NAND memory device includes blocks of single-level cell (SLC) memory and multi-level cell (MLC) memory storing n-bits per cell such as quad-level cell (QLC) or penta-level cell (PLC) memory. The NAND memory device further includes a plurality of page buffer latches and logic to copy data from a set of n SLC pages in a block of SLC memory into n respective page buffer latches and copy data from the respective page buffer latches to an MLC page (e.g., QLC or PLC page) in a block of MLC memory. These operations can be extended for NAND memory devices having multiple planes with blocks of SLC and QLC/PLC memory. QLC/PLC program and program-resume operations are supported with optional ECC correction operations.