NAND Flash Copyback Error Detection and Correction
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Solution Overview
Problem
In NAND flash data storage systems, copyback operations can accumulate un-repairable data errors due to internal data transmission errors being unnoticed by users, leading to potential data corruption over time.
Innovation Solution
A data storage system comprising a first memory, a controller, a counting module, and a checking and correcting module, which performs counting operations on copyback operations at different logic addresses to determine if data needs to be checked and corrected, using techniques such as frequency indicators or error checking and correcting codes to ensure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copyback operations are performed in NAND flash without error detection, then data transmission speed is improved and device complexity is reduced, but data reliability deteriorates due to accumulated un-repairable errors
Solution Approach 1:
The patent implements error detection and correction mechanisms that provide feedback about data integrity status. The system monitors copyback operations and triggers corrective actions when errors are detected, creating a closed-loop system that maintains reliability without requiring complete redesign of the storage architecture.
Solution Approach 2:
The patent employs preliminary error detection codes and validation mechanisms that are applied before data corruption becomes critical. By performing error checking in advance and preparing correction data, the system prevents un-repairable errors from accumulating while maintaining operational efficiency.
2Stability of the object's composition
If frequent copyback operations are performed to maintain data, then data freshness is improved, but data reliability deteriorates due to accumulated transmission errors
Solution Approach 1:
The system incorporates feedback mechanisms that monitor the quality of copyback operations and adjust subsequent operations based on detected errors. When errors are identified, the system modifies future copyback operations to prevent similar issues, maintaining data integrity while reducing harmful repeated operations.
Solution Approach 2:
The patent changes operational parameters such as error detection thresholds, correction codes, and validation frequencies based on the detected error patterns. By dynamically adjusting these parameters, the system maintains optimal balance between data freshness and reliability without fixed rigid rules.
3Reliability
If error checking and correcting operations are implemented, then data reliability is improved, but device complexity and operation time increase
Solution Approach 1:
The patent applies partial error checking and correcting operations only when and where necessary, rather than continuously checking all data. By using selective validation and threshold-based triggers, the system performs sufficient error detection to maintain reliability while avoiding excessive operations that would waste time.
Solution Approach 2:
The system performs preliminary error detection setup and maintains correction capabilities in advance, so that when errors occur, correction can be applied quickly without requiring time-consuming analysis. The preliminary preparation of correction mechanisms reduces actual error correction time.
Data Source
AI summary
A data storage system includes a first memory, a controller, a counting module, and a checking and correcting module. Copyback operations are performed in the first memory. The controller couples the first memory to the counting module and the checking and correcting module. The counting module provides a counting operation for the copyback operations at different logic addresses of the first memory and, according to a counting result of the counting operation, determines whether a checking and correcting requirement has been satisfied by any of the logic addresses. The checking and correcting module receives data read out from the first memory, wherein the received data corresponds to a satisfying logic address, and checks the received data and corrects the received data when it is checked that the received data is incorrect, to correct the first memory accordingly.