NAND Flash Copy-Back Parity Reloading for 2-Bit Error Prevention
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Solution Overview
Problem
Conventional NAND flash memory devices generate 2-bit errors during copy back program operations, which cannot be corrected by the memory controller, leading to data integrity issues.
Innovation Solution
A NAND flash memory device with a cell array, parity cell array, and parity generation and column selection circuits that generate and program new parity data during the copy back program operation, enabling error detection and data reloading to prevent 2-bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If copy back program operation is performed to improve programming speed, then productivity is improved, but reliability deteriorates due to generation of 2-bit errors
Solution Approach 1:
The patent performs error detection and parity verification before completing the copy back program operation. By detecting errors in advance and preventing programming of erroneous data, the system maintains high reliability while preserving the speed benefits of copy back operation. The memory controller checks parity of source page data before copying to target page, and verifies during the operation to prevent 2-bit errors.
2Loss of time
If conventional copy back program operation is used to omit reading and external reloading, then time is saved, but harmful factors increase due to uncorrectable 2-bit errors
Solution Approach 1:
The patent implements a feedback mechanism where the memory controller continuously monitors the copy back program operation by checking parity bits. When an error is detected during the operation, the controller can interrupt and correct the error before it becomes uncorrectable. This feedback loop eliminates harmful 2-bit errors while maintaining the time efficiency of the copy back operation.
3Device complexity
If no error detection is performed during copy back operation, then device complexity is reduced, but reliability deteriorates
Solution Approach 1:
The memory device performs self-diagnosis and self-correction during the copy back program operation through automatic parity checking. The memory controller independently detects and corrects errors without requiring external intervention, thereby maintaining operational simplicity while significantly improving reliability. The system serves itself by detecting and correcting 2-bit errors that would otherwise be uncorrectable.
Data Source
AI summary
A NAND flash memory device performing an error detecting and data reloading operation during a copy back program operation is provided. The device includes a cell array having a plurality of planes and a parity cell array having a plurality of parity planes. Each of the parity planes stores a parity of each of the planes. Additionally, the device includes a parity generating and parity column selecting circuit generating a new parity about reloaded data from an outside during a copy back program operation, and storing the new parity on a parity plane corresponding to a plane on which the reloaded data is stored.