Continuous NAND Data Transfer via Buffer Rate Evaluation
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Solution Overview
Problem
Existing data storage devices, such as solid state drives (SSDs), face increased latency and additional system requirements due to pausing data input/output operations, which disrupt continuous data-transfer processes.
Innovation Solution
A controller in the data storage device delivers a continuous DQS signal, evaluates buffer fill/emptying rates, and separates user and garbage data for seamless transfer, ensuring continuous data flow by scheduling data transfers based on buffer fullness and rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data input/output operations are paused to manage buffer levels, then buffer overflow/underflow is prevented, but latency increases and continuous data-transfer is disrupted
Solution Approach 1:
The patent maintains continuous DQS signal toggling and continuous data bus activity without pausing, ensuring that data transfer operations never stop. The controller continuously evaluates buffer fullness and dynamically adjusts data transfer timing to match buffer consumption/production rates, eliminating idle periods and maintaining uninterrupted useful action throughout the data transfer process.
Solution Approach 2:
The controller implements a feedback mechanism by continuously monitoring buffer fullness levels and using this information to dynamically adjust the timing and rate of data transfers. This closed-loop control ensures that data is transferred at optimal rates to prevent buffer overflow or underflow while maintaining continuous operation, thereby resolving the contradiction between reliability and latency.
2Productivity
If bigger buffers are incorporated in read/write paths to prevent pausing, then continuous data-transfer is maintained, but device complexity and system requirements increase
Solution Approach 1:
Instead of using statically large buffers, the patent employs dynamically adjustable data transfer rates controlled by the controller. The controller adapts the timing and speed of data transfers based on real-time buffer status, allowing smaller buffers to operate effectively without overflow or underflow. This dynamic control replaces the need for oversized static buffers, reducing device complexity while maintaining continuous data transfer capability.
Solution Approach 2:
The patent changes the operational parameters of data transfer by continuously adjusting transfer timing and rate based on buffer fullness evaluation. Rather than increasing buffer capacity, the system modifies transfer parameters (timing, frequency, rate) to optimize buffer utilization, thereby maintaining productivity without increasing device complexity or buffer size.
3Reliability
If DQS signal is paused to pause data-transfer, then data integrity is maintained, but latency increases and continuous operation is broken
Solution Approach 1:
The patent maintains continuous DQS signal toggling throughout the entire data transfer process, never pausing the clock signal. Data integrity is preserved not by pausing the signal but by ensuring data is transferred at appropriate timing relative to buffer status. The continuous DQS signal drives continuous data bus activity, eliminating idle periods while maintaining synchronization and data integrity through controlled transfer timing.
Data Source
AI summary
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to deliver a continuous DQS signal, determine whether a fill rate of a write buffer or an emptying rate of read buffer is sufficient to continuously send user data to the memory device or from the memory device, evaluate timing for sending or receiving the user data, and transfer data to or from the memory device continuously with the DQS signal. The data sent to the memory device includes the user data and garbage data, where the user data and the garbage data are separately transferred. The data received from the memory device includes user data that is sampled and user data that is not sampled, where the user data that is sampled and the user data that is not sampled are separately received.