3D NAND Deck Interconnection Structure for Multi-Step Via Etching
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Solution Overview
Problem
The challenge in stacking multiple deck structures for three-dimensional NAND memory devices lies in the compatibility issues and increased difficulty due to large aspect ratios of through silicon vias formed by single etching processes, which complicates the etching process and reduces compatibility with different wafers.
Innovation Solution
A semiconductor structure and fabrication method involving multiple etching steps to form interconnection structures, where contacts penetrate through stack structures and are bonded to form deck structures, reducing the complexity of the etching process and improving compatibility by using different etching parameters for various materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If single etching process is used to form through silicon vias, then the aspect ratio is large, but the etching process becomes more difficult and compatibility with different wafers is reduced
Solution Approach 1:
The patent divides the single etching process into multiple etching steps, where each step etches through a portion of the stack structure. This segmentation reduces the aspect ratio for each individual etching step, making the process more manageable and compatible with different wafer materials. The multi-step approach allows optimization of etching parameters for each specific material layer encountered.
Solution Approach 2:
The patent employs different etching parameters for different material layers during the multi-step etching process. By adjusting etching chemistry, power, pressure, and other parameters according to the specific material being etched (silicon, oxide, nitride, etc.), the process achieves high compatibility across diverse wafer compositions while maintaining precise control over via formation.
2Quantity of substance
If multiple deck structures are stacked, then the storage density increases, but the manufacturing complexity increases
Solution Approach 1:
The patent segments the manufacturing process into modular steps that can be repeated for each deck structure. The multi-step etching and bonding sequence is applied systematically to stack multiple decks, where each deck undergoes the same standardized process sequence. This modular approach increases storage density through stacking while keeping the manufacturing complexity manageable through process standardization.
Solution Approach 2:
The patent performs preliminary preparation of contact structures and etching of vias in each stack structure before the bonding step. By preparing all necessary features in advance on separate wafers before stacking, the actual bonding process becomes simpler and more reliable. This preliminary action allows complex features to be formed under optimized conditions for each individual wafer, then combined through relatively simple bonding operations.
Data Source
AI summary
Examples of the present disclosure propose a semiconductor structure and a fabrication method thereof, a memory device, and a memory system. The semiconductor structure includes at least one deck structure. The fabrication method of the deck structure includes: providing a first stack structure in which a peripheral circuit is disposed; forming a first contact and a second contact at least penetrating through the first stack structure; providing a second stack structure in which a memory cell array is disposed; forming a third contact and a fourth contact penetrating through the second stack structure; stacking and bonding the first stack structure and the second stack structure along a first direction to form the deck structure, wherein the first contact is connected with the third contact by bonding to form a first interconnection structure, and the second contact is connected with the fourth contact by bonding to form a second interconnection structure.