3D NAND Defect Cell Detection via Floating Word-Line Sensing
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Solution Overview
Problem
Flash memory devices face increased erroneous data bits due to leakage currents caused by channel hole breakouts, which prevent threshold voltages of memory cells from being changed to target values, affecting data retention and reliability.
Innovation Solution
A nonvolatile memory device with a defect cell detection method that applies a setting voltage to word lines, floats them to sense voltage changes, and counts off-cells to identify defect cells, allowing for the processing of defective blocks as bad blocks to ensure data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flash memory devices operate without defect detection, then device complexity is reduced, but reliability deteriorates due to channel hole breakouts causing leakage currents and erroneous data bits
Solution Approach 1:
The patent implements preliminary defect detection by applying a setting voltage to word lines and floating them during a floating time period before normal operation. This preliminary action identifies defect cells (off-cells) by sensing voltage changes on bit lines, allowing the system to detect channel hole breakouts before they cause data corruption, thereby improving reliability without requiring complex real-time monitoring circuits
Solution Approach 2:
The defect detection mechanism utilizes the memory device's own existing circuits (word lines, bit lines, page buffer circuit) to perform self-diagnosis. By applying setting voltages and sensing voltage changes through the existing read path, the system detects defect cells using its own infrastructure, avoiding the need for separate complex detection circuits while maintaining reliability
2Reliability
If defect detection operations are performed frequently, then reliability is improved, but productivity deteriorates due to additional operation time
Solution Approach 1:
The patent implements periodic defect detection by performing the detection operation at predetermined intervals or under specific conditions (e.g., after program operations, before read operations). The row decoder applies setting voltages to word lines periodically, and the page buffer circuit senses voltage changes at these periodic intervals, balancing reliability improvement with minimal impact on overall memory throughput by not performing detection continuously
Solution Approach 2:
The defect detection operation is performed partially by selecting specific word lines for detection based on usage patterns or error rates. The row decoder applies setting voltages to selected word lines rather than all word lines simultaneously, and the detection is performed on a per-page or per-block basis, reducing the overall time penalty while maintaining adequate reliability coverage
Data Source
AI summary
A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.