NAND Die Queue Fill Level Monitoring for Cached Command Selection

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Solution Overview

Problem

In high-performance NAND systems, data processing bottlenecks occur due to incorrect decisions between using cached or non-cached read commands, as existing methods struggle to efficiently determine the optimal choice based on dynamic factors such as queue fill status, leading to suboptimal performance.

Innovation Solution

A method and system where a data storage controller assesses the fill status of a memory access queue to determine whether to use cached or non-cached memory access operations, by comparing the number of entries in the queue against predetermined thresholds, allowing for intelligent and efficient decision-making on a die-by-die basis.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If cached read commands are employed, then read performance is improved, but data processing bottlenecks occur when queue fill status is inappropriate

Engineering Contradiction:
Improveread performanceVSAvoiddata processing efficiency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system dynamically adjusts between cached and non-cached read commands based on the real-time fill status of the memory access queue. When the queue fill status indicates available capacity, cached commands are used to maximize read performance. When the queue is nearly full, the system switches to non-cached commands to prevent bottlenecks, ensuring reliable data processing under varying conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The die manager continuously monitors the fill status of the memory access queue and uses this feedback to make intelligent decisions about command selection. This closed-loop control ensures that the system adapts to changing queue conditions, optimizing read performance while avoiding processing bottlenecks by switching between cached and non-cached commands based on actual queue state.

Inventive Principle:
Principle #23Feedback

2Reliability

If non-cached read commands are employed, then data processing reliability is improved, but read performance deteriorates when cached commands would be more efficient

Engineering Contradiction:
Improvedata processing efficiencyVSAvoidread performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system dynamically switches between non-cached and cached commands based on queue fill status. When the queue is nearly full, non-cached commands are used to ensure reliable data processing and avoid bottlenecks. When the queue has available capacity, the system transitions to cached commands to maximize read performance, thus adapting to conditions in real-time.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the operational parameter of read command type (cached vs. non-cached) based on the queue fill status parameter. This parameter change allows the system to optimize between reliability and performance by selecting the appropriate command mode according to the current state of the memory access queue.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If cached commands are used without queue status assessment, then read performance is maximized, but bottlenecks occur in the die manager or data path

Engineering Contradiction:
Improveread performanceVSAvoidprocessing bottleneck
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The die manager performs a preliminary assessment of the queue fill status before issuing cached read commands. This advance check prevents bottlenecks by ensuring that the queue has sufficient capacity to handle cached commands. By evaluating queue status beforehand, the system avoids the complexity of processing bottlenecks while maintaining high read performance when conditions are favorable.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses feedback from queue fill status monitoring to control the issuance of cached commands. This feedback mechanism prevents bottlenecks by stopping cached command issuance when the queue is nearly full, thus avoiding the need for complex bottleneck handling while maintaining optimal performance through intelligent command selection.

Inventive Principle:
Principle #23Feedback

4Device complexity

If non-cached commands are used without queue status assessment, then bottlenecks are avoided, but read performance suffers when cached commands would be optimal

Engineering Contradiction:
Improveprocessing bottleneckVSAvoidread performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The die manager performs a preliminary assessment of queue fill status before deciding between cached and non-cached commands. This advance evaluation ensures that cached commands are used when they will be optimal (queue has capacity), preventing performance loss. The preliminary check avoids unnecessary use of non-cached commands while maintaining simplicity by preventing bottlenecks through intelligent decision-making.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes the command type parameter based on queue fill status assessment. When the queue has available capacity, the parameter switches to cached commands to maximize performance. When the queue is full, it switches to non-cached commands to avoid bottlenecks, thus optimizing read performance without the complexity of handling bottlenecks through simple parameter adjustment.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10642746B2Controlling cached/non-cached memory access decisions based on memory access queue fill levels
Publication Date: 2020.05.05 SANDISK TECHNOLOGIES LLC
  • US10642746B2 patent drawing
  • US10642746B2 patent drawing
  • US10642746B2 patent drawing

AI summary

The present disclosure, in various embodiments, describes technologies and techniques for use by a data storage controller or similar device for efficiently and intelligently determining whether to use cached or non-cached memory access commands when accessing a non-volatile memory (NVM) device, such as a particular die of a multi-die NAND flash memory. In some examples, the data storage controller assesses the fill status of a particular memory access die queue (e.g., whether the queue is mostly full or mostly empty) and then determines whether to submit memory access commands to a NAND die as cached operations or non-cached operations based on the assessed fill status. In illustrative examples, the determination is made by a die manager based on the number of entries in the queue, with cached commands used if the entries exceed a predetermined threshold, and non-cached commands used otherwise. Method, system and apparatus examples are provided herein.