NAND Die Reordering Logic for SSD Contention Reduction

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Solution Overview

Problem

In memory systems, particularly in solid-state drives (SSDs) with multiple NAND die, contention between host and background data writes leads to delays and resource bottlenecks, affecting quality-of-service (QoS) metrics like throughput, latency, and performance consistency, due to sequential dispatching and resource competition.

Innovation Solution

Implementing a logic system that determines a differentiator for access requests to randomly reorder the target order of NAND die, excluding parity die from reordering, thereby reducing consecutive collisions and optimizing resource allocation across multiple NAND die for parallel write operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If sequential dispatching is used for host and background writes to NAND die, then resource allocation is simplified, but die contention increases causing delays and performance degradation

Engineering Contradiction:

Improveresource allocation complexityVSAvoidwrite throughput

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent implements dynamic die ordering where the target order of NAND die is randomly reordered based on a differentiator (such as LBA range or stream identifier). This dynamic reordering allows the system to adaptively change die assignment for different write streams, preventing consistent contention patterns between host and background writes while maintaining flexible resource allocation.

Inventive Principle:

Principle #15Dynamics

2Stability of the object's composition

If fixed target order of NAND die is used, then die assignment is deterministic, but consecutive collisions between host and background writes occur causing latency increases

Engineering Contradiction:

Improvedie assignment consistencyVSAvoidwrite latency

Core Design Contradiction:

Stability of the object's compositionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by determining the differentiator for each access request before dispatching the write operation. Based on this differentiator, the system pre-determines a random target order for NAND die, ensuring that host writes and background writes are assigned to different die sequences before the actual write operations begin, thereby preventing consecutive collisions and reducing latency.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If random reordering of NAND die is applied to all access requests, then die contention is reduced, but system complexity and overhead increase

Engineering Contradiction:

Improvewrite performanceVSAvoidmapping logic complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent applies local quality by selectively reordering die based on the differentiator. Instead of uniformly reordering all die for all access requests, the system determines whether reordering is needed based on the specific access request characteristics (such as LBA range or stream identifier). This selective approach reduces unnecessary complexity while maintaining the contention-reduction benefits where needed.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS10585791B2Ordering of memory device mapping to reduce contention

Publication Date: 2020.03.10 INTEL NDTM US LLC

AI summary

An embodiment of a semiconductor apparatus may include technology to determine a differentiator associated with an access request for two or more memory devices, and set a target order for the two or more memory devices based on the differentiator. Other embodiments are disclosed and claimed.