NAND Die Sleep-Wakeup Control for Leakage and Surge Current
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Solution Overview
Problem
The accumulation of leakage current across multiple dies in a NAND flash memory device leads to surge current, which can damage the host system and cause data integrity and performance issues, as existing methods to manage die states add overhead and impact performance.
Innovation Solution
A memory device executes automatic wakeup and sleep sequences for individual dies based on the status of other dies using processor-controlled interrupt numbers and broadcast commands, minimizing overhead and preventing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the controller manually monitors and issues sleep/wakeup commands to each die, then leakage current is reduced, but device complexity and operational overhead increase
Solution Approach 1:
Each die includes a local processor that autonomously determines its own sleep/wakeup state by monitoring IO line transitions related to other dies. The die independently executes sleep sequences or wakeup sequences based on detected transitions, eliminating the need for the controller to manually monitor and command each die, thus reducing controller overhead while maintaining leakage current reduction
Solution Approach 2:
The centralized controller function is segmented and distributed to individual dies. Each die has its own processor that handles sleep/wakeup control locally, rather than having a single controller manage all dies. This distribution reduces the operational burden on the controller and enables parallel autonomous decision-making at the die level
2Loss of energy
If the controller manually manages sleep/wakeup states of multiple dies, then leakage current is controlled, but productivity and performance are impacted
Solution Approach 1:
Dies autonomously manage their own sleep/wakeup transitions by detecting IO line transitions, eliminating the time overhead associated with controller monitoring and command issuance. This self-service mechanism reduces latency and improves performance while maintaining leakage current control
Solution Approach 2:
The system uses event-triggered periodic monitoring where each die processor continuously monitors IO lines for transitions. This event-driven approach allows dies to remain in low-power states longer and transition quickly when needed, improving overall productivity compared to continuous controller monitoring
3Speed
If multiple dies operate simultaneously without coordination, then data write speed increases, but surge current accumulates and may damage the host
Solution Approach 1:
Each die processor monitors IO lines that reflect the operational state of other dies. When a transition is detected indicating another die is entering or leaving active state, the monitoring die adjusts its own state accordingly. This feedback mechanism coordinates die operations to prevent simultaneous activation that would cause surge current, while still enabling parallel data writes when safe
Solution Approach 2:
Before a die transitions to an active state, its processor first monitors IO lines to detect transitions indicating other dies are already active or becoming active. This preliminary monitoring prevents the die from transitioning at a time that would create surge current conditions, allowing coordinated parallel operations when safe
Data Source
AI summary
A die on a memory device enters a wakeup or sleep state based on statuses of other dies on the memory device. The die includes an input/output (IO) line to indicate its operation state. A processor on the die obtains a wakeup interrupt die number and a sleep interrupt die number set by a storage device connected to the memory device. The processor receives a broadcast command including IO statuses for IO lines associated with the other dies on the memory device. The processor determines when an IO line for a second die associated with the wakeup interrupt die number transitions from a 1 state to a 0 state and executes a wakeup sequence. The processor also determines when an IO line for a third die associated with the sleep interrupt die number transitions from the 0 state to the 1 state and executes a sleep sequence.