NAND Memory Error Recovery Using Dual Buffer Segmentation

Solution Overview

Problem

NAND flash memory systems face challenges in error recovery due to high program latencies and host data rates, which exceed the capacity of on-chip buffer memory, often requiring large external buffer memories that increase power consumption and cost.

Innovation Solution

A system utilizing both on-chip and off-chip buffer memories, where program data is split and sent to both buffers in parallel, with circular buffers for efficient data storage and recovery, allowing for error detection and recovery without continuous external buffer memory usage, thus reducing external data path requirements and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a large external buffer memory is used to accommodate re-written data during NAND program operations, then error recovery capability is improved, but power consumption and device cost increase

Engineering Contradiction:

Improveerror recovery capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the buffer memory into two parts: a small on-chip buffer (internal buffer) and a larger off-chip buffer (external buffer). The internal buffer handles frequent, small data transfers during normal operation, while the external buffer provides additional capacity for error recovery scenarios. This segmentation allows the system to achieve reliable error recovery without continuously engaging the high-power external buffer, thus resolving the contradiction between reliability and power consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by pre-buffering program data in both internal and external buffers before NAND program operations commence. This allows the system to have recovery data ready in advance, eliminating the need for high-speed external buffer access during error recovery scenarios. The preliminary buffering action reduces the power consumption during error recovery while maintaining the ability to rewrite failed data elements.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If a large external buffer memory is used to accommodate re-written data during NAND program operations, then error recovery capability is improved, but device cost increases

Engineering Contradiction:

Improveerror recovery capabilityVSAvoiddevice cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the buffer memory into two parts: a small on-chip buffer (internal buffer) and a larger off-chip buffer (external buffer). The internal buffer handles frequent, small data transfers during normal operation, while the external buffer provides additional capacity for error recovery scenarios. This segmentation allows the system to achieve reliable error recovery without continuously engaging the high-power external buffer, thus resolving the contradiction between reliability and power consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by using the external buffer only when necessary for error recovery, rather than continuously. The system maintains a smaller internal buffer for normal operations and selectively activates the external buffer capacity only when program errors occur and data rewriting is needed. This partial utilization reduces the overall buffer size requirements and associated costs while maintaining error recovery capability.

Inventive Principle:

Principle #16Partial or excessive action

3Use of energy by moving object

If on-chip buffer memory is used for error recovery, then power consumption is reduced, but the buffer capacity is insufficient for high host data rates

Engineering Contradiction:

Improvepower consumptionVSAvoidbuffer capacity

Core Design Contradiction:

Use of energy by moving objectVSQuantity of substance

Solution Approach 1:

The patent segments the buffer memory into two parts: a small on-chip buffer (internal buffer) and a larger off-chip buffer (external buffer). The internal buffer handles frequent, small data transfers during normal operation, while the external buffer provides additional capacity for error recovery scenarios. This segmentation allows the system to achieve reliable error recovery without continuously engaging the high-power external buffer, thus resolving the contradiction between reliability and power consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic buffer management where the system adapts between internal and external buffer usage based on operational needs. During normal high-speed data transfers, the system primarily uses the low-power internal buffer. When program errors occur requiring data rewriting, the system dynamically activates the external buffer to provide the necessary additional capacity. This dynamic switching resolves the contradiction between power consumption and buffer capacity.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS10901868B1Systems and methods for error recovery in NAND memory operations

Publication Date: 2021.01.26 MARVELL ASIA PTE LTD

AI summary

Embodiments described herein provide a mechanism to use an on-chip buffer memory in conjunction with an off-chip buffer memory for interim NAND write data storage. Specifically, the program data flows through the on-chip buffer memory to the NAND memory, while simultaneously a copy of the NAND program data is buffered in one or more circular buffer structures within the off-chip buffer memory.