3D NAND Dummy Cell Wiring for Faster Defect Detection

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Solution Overview

Problem

The existing semiconductor memory technologies face challenges in efficiently detecting defects and ensuring high reliability while maintaining low costs and short testing times, particularly in three-dimensionally structured NAND flash memory systems.

Innovation Solution

The implementation of multiple dummy regions connected by common wiring allows for simultaneous testing and defect detection, reducing the complexity and time required for testing, and preventing the collapse of the stack structure during manufacturing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple dummy regions are tested separately in three-dimensionally structured NAND flash memories, then defect detection coverage is improved, but testing time and cost increase

Engineering Contradiction:

Improvedefect detection coverageVSAvoidtesting time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent connects multiple dummy regions (first dummy region and second dummy region) through common bit lines and word lines, allowing simultaneous voltage application and defect detection across all dummy regions. This merging of testing operations maintains comprehensive defect detection coverage while reducing total testing time by eliminating sequential testing requirements

Inventive Principle:

Principle #5Merging (Combining)

2Measurement precision

If multiple dummy regions are tested separately, then defect detection accuracy is improved, but manufacturing cost increases

Engineering Contradiction:

Improvedefect detection accuracyVSAvoidmanufacturing cost

Core Design Contradiction:

Measurement precisionVSEase of manufacture

Solution Approach 1:

By sharing common bit lines and word lines across multiple dummy regions, the patent reduces the total number of required wiring structures and testing operations. This merging approach maintains defect detection accuracy through comprehensive coverage while lowering manufacturing costs by reducing material usage and process complexity

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The common bit lines and word lines serve multiple functions: they are used for both normal memory cell operations and for defect detection in dummy regions. This multi-functionality eliminates the need for separate dedicated testing structures, thereby reducing manufacturing cost while maintaining detection accuracy

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Difficulty of detecting and measuring

If separate wiring is used for each dummy region, then defect detection capability is improved, but device complexity increases

Engineering Contradiction:

Improvedefect detection capabilityVSAvoidwiring complexity

Core Design Contradiction:

Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The patent merges the wiring structures by having multiple dummy regions share common bit lines and word lines. This approach maintains full defect detection capability across all dummy regions while significantly reducing device complexity by eliminating redundant wiring, thereby simplifying the overall memory structure

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20240251561A1Semiconductor memory

Publication Date: 2024.07.25 KIOXIA CORP

AI summary

A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.