Hybrid Polar-BCH ECC Switching for NAND Read Latency

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Solution Overview

Problem

NAND memory devices face challenges in achieving high read throughput and low latency with low power consumption and complexity, necessitating effective error correction codes (ECCs) that balance complexity and performance across hard decision (HD) and soft decision (SD) channels.

Innovation Solution

A combination of BCH-GCC and Polar-GCC codes is employed, leveraging the strengths of both for HD channels with low complexity and SD channels with high coverage, utilizing decoding algorithms tailored for ECC schemes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If algebraic codes (BCH, RS, BCH-GCC) are used for HD channels, then complexity is reduced, but error correction capability for soft decision channels is insufficient

Engineering Contradiction:

Improvedecoder complexityVSAvoiderror correction capability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent merges BCH-GCC and Polar-GCC codes into a hybrid ECC scheme where BCH-GCC handles hard decision decoding with low complexity while Polar-GCC provides enhanced soft decision error correction capability. The decoding architecture integrates both decoders working in coordination to achieve both low complexity and high reliability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements dynamic decoding mode selection where the system can switch between HD mode (using BCH-GCC decoder) and SD mode (using Polar-GCC decoder) based on channel conditions and error patterns. This dynamic adaptation allows the system to optimize between complexity and error correction capability depending on operational requirements.

Inventive Principle:

Principle #15Dynamics

2Reliability

If multiple reads are performed from NAND to improve error correction, then error correction capability increases, but read throughput decreases and latency increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidread throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies partial action by performing error correction on only the necessary portions of data using the hybrid BCH-GCC/Polar-GCC scheme. The system uses BCH-GCC for initial HD decoding which corrects many errors without requiring additional reads, and only invokes Polar-GCC soft decision decoding when needed, thus avoiding the throughput penalty of multiple reads while maintaining high error correction capability.

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If soft decision decoding is used to improve error correction, then error correction capability increases, but power consumption and complexity increase

Engineering Contradiction:

Improveerror correction capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The hybrid ECC scheme provides self-service by having BCH-GCC handle the majority of error correction cases with low power consumption, and automatically invoking Polar-GCC soft decision decoding only when BCH-GCC fails to correct errors. This tiered approach allows the system to serve its own error correction needs efficiently without consistently incurring the high power cost of SD decoding.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS20260003728A1Polar-BCH combined generalized concatenated codes

Publication Date: 2026.01.01 SAMSUNG ELECTRONICS CO LTD

AI summary

A nonvolatile memory device includes a memory and processing circuitry configured to receive a read request from a host, read an ECC noisy codeword from the memory based on the read request, determine to decode the ECC noisy codeword using a first decoder or a second decoder, and decode the ECC noisy codeword using the determined decoder.