NAND ECC Chip Segmentation for SPI Idle Reduction
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Solution Overview
Problem
In NAND-type flash memory, the narrow bit width of the DO terminal of the SPI interface leads to prolonged idle states in the controller chip, limiting pipeline processing performance and increasing chip size due to the large area occupied by the page buffer/sensing circuit, especially with high integration of memory arrays.
Innovation Solution
A semiconductor storage device configuration with a NAND chip and an ECC chip, where the second latch of the page buffer/sensing circuit has a smaller data size than the first latch, and the ECC chip is separated from the NAND chip to enable high-speed error detection and correction, optimizing data transmission through a wider DATA terminal with a larger bit width, allowing faster processing and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the SPI interface with narrow bit width is used for data transmission, then the existing interface structure can be maintained, but the idle state of the controller chip is prolonged and pipeline processing performance is limited
Solution Approach 1:
The data transmission path is segmented into two channels: the original SPI interface for control signals and a new parallel DATA terminal for high-speed data transmission. This segmentation allows data to be transmitted in parallel with control operations, eliminating the bottleneck of sequential SPI transmission and reducing controller idle time.
Solution Approach 2:
A dedicated DATA terminal acts as an intermediary channel between the NAND chip and controller, specifically designed for high-speed data transmission. This intermediary path bypasses the limitations of the SPI interface, enabling simultaneous data transfer and control signaling without interfering with each other.
2Quantity of substance
If the page buffer/sensing circuit area is increased to accommodate larger latch capacity, then data holding capacity is improved, but the chip size increases
Solution Approach 1:
The ECC function is extracted from the NAND chip and placed on a separate chip. This extraction removes the need for large page buffer/sensing circuits on the NAND chip, as error correction processing is offloaded to the external ECC chip, thereby reducing the chip area while maintaining data holding capacity.
Solution Approach 2:
The data holding and processing function is extended to another dimension by using a separate ECC chip. Instead of increasing the area of the NAND chip, the system uses spatial separation to accommodate the processing requirements, allowing the NAND chip to remain compact while the ECC chip handles the computational tasks.
3Productivity
If the ECC function is integrated on the same chip as the NAND array, then data transmission distance is reduced, but the chip size and processing complexity increase
Solution Approach 1:
The system is segmented into two specialized chips: a NAND chip for data storage and a separate ECC chip for error correction processing. This segmentation allows each chip to be optimized for its specific function, increasing processing speed while distributing complexity across separate components rather than concentrating it in a single large chip.
Solution Approach 2:
The ECC processing capability is implemented as a separate but functionally coupled system. The ECC chip receives data from the NAND chip through the parallel interface and performs error correction, effectively creating a distributed processing architecture that maintains functional integration while reducing individual chip complexity.
Data Source
AI summary
The disclosure provides a semiconductor storage device and a reading method, which may achieve high-speed processing time for error detection and correction and achieve miniaturization. The flash memory of the disclosure has a NAND chip and an ECC chip. The NAND chip has: a memory array; a page buffer/sensing circuit, including latches L1 and L2; and dedicated input and output terminals, which may be used for data transmission with ECC chip. The latch L1 contains cache C0 and cache C1, and the latch L2 only contains the cache C1. The data in the cache C0 of the latch L1 and the data in the cache C1 of the latch L2 are transmitted to the ECC chip. In response to outputting data at the initial address from the ECC chip, the next page is read from the memory array, and the read data is held in the latch L1.