NAND EEPROM Air Gaps Reduce Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In nonvolatile semiconductor memory devices, such as NAND-type flash memory, the shortening of bit line distances leads to increased parasitic capacitance between adjacent gate electrodes, resulting in decreased write speed, particularly for memory cell transistors with gate lengths in the 10 nm range or smaller.
Innovation Solution
The introduction of air gaps between adjacent floating gate electrodes, formed by removing a part of the buried insulating film and extending them below the control gate electrode, reduces parasitic capacitance and fringe capacitance, thereby improving the coupling ratio and write voltage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell is made finer to achieve larger packing densities, then packing density is improved, but parasitic capacitance between adjacent gate electrodes increases
Solution Approach 1:
The patent extracts the harmful dielectric material between adjacent floating gate electrodes and replaces it with air gaps. By removing the insulating film in specific regions and forming air gaps between the floating gates, the parasitic capacitance is reduced while maintaining the fine pitch structure needed for high packing density.
Solution Approach 2:
The patent changes the dielectric parameter between adjacent floating gate electrodes from a solid insulator (with higher dielectric constant) to air (with dielectric constant of approximately 1). This parameter change reduces the parasitic capacitance between adjacent gates, enabling finer memory cell structures to achieve larger packing densities without suffering from excessive parasitic capacitance.
2Length of moving object
If gate length is reduced to 10 nm or smaller, then memory cell size is reduced, but write speed decreases due to increased parasitic capacitance
Solution Approach 1:
The patent removes the insulating film between adjacent floating gate electrodes and introduces air gaps in its place. This extraction of the harmful dielectric material reduces parasitic capacitance and fringe capacitance, thereby improving write speed even when the gate length is reduced to 10 nm or smaller.
Solution Approach 2:
By changing the dielectric parameter between adjacent floating gates from a solid insulator to air, the patent reduces parasitic capacitance effects. This parameter change allows the memory device to maintain faster write speeds despite the reduced gate length of 10 nm or smaller, as the lower parasitic capacitance reduces the capacitive loading on the control gates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, shortens the distribution width of threshold voltages, and enhances write speed by utilizing air gaps with a lower dielectric constant compared to traditional insulators, improving the performance of memory cell transistors.
Implementation Method 1
utilizing air gaps with a lower dielectric constant compared to traditional insulators, improving the performance of memory cell transistors
Data Source
AI summary
According to one embodiment, a part of a buried insulating film buried in a trench is removed; accordingly, an air gap is formed between adjacent floating gate electrodes in a word line direction, and the air gap is formed continuously along the trench in a manner of sinking below a control gate electrode.