3D NAND Gate Electrode Layout Without Staircase Contacts
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Solution Overview
Problem
The increasing demand for high-performance semiconductor devices with high integration and multi-functionality necessitates the formation of fine patterns and narrow separation distances, which poses challenges in manufacturing processes.
Innovation Solution
A semiconductor device design that includes a stack structure with gate electrodes, channel structures, and insulating regions, allowing for the formation of contact plugs without a staircase process, thereby increasing the available area for memory regions and improving integration by enabling simultaneous selection of memory regions on both sides of gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a staircase process is used to form contact regions of gate electrodes, then contact alignment is improved, but manufacturing complexity and process steps increase
Solution Approach 1:
The patent removes the staircase process step entirely from the manufacturing sequence. Contact plugs are formed to directly contact the gate electrodes at their natural endpoints without requiring the gate electrodes to be shaped into staircase configurations, thereby simplifying the process while maintaining contact alignment
Solution Approach 2:
Instead of shaping the gate electrodes into staircase forms to facilitate contact formation, the patent inverts the approach by forming contact plugs that naturally align with and contact the gate electrode endpoints, eliminating the need for complex gate electrode shaping
2Reliability
If gate electrodes extend continuously across memory regions, then electrical connection is improved, but available area for memory regions decreases
Solution Approach 1:
The gate electrodes are segmented into discrete sections by insulating regions that separate them. This segmentation allows contact plugs to access specific gate electrode endpoints while insulating regions prevent unwanted electrical connections, maintaining electrical connection reliability where needed while freeing up area for memory regions
Solution Approach 2:
Insulating regions are introduced as intermediary elements between gate electrode sections. These insulating regions serve as mediators that provide electrical isolation where required, enabling the gate electrodes to be discontinuous while still maintaining proper electrical connections through contact plugs at designated locations
3Productivity
If fine patterns are formed to increase integration, then degree of integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the geometric parameters of the contact plugs and gate electrodes to optimize their dimensions and positions. By carefully controlling the size and placement parameters, the design achieves high integration while maintaining manufacturability with standard precision capabilities
Data Source
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AI summary
A semiconductor device (100) according to an example embodiment may include a conductive layer (101), a stack structure (GS) including lower gate electrodes (130L), memory gate electrodes (130M), and upper gate electrodes (130U) stacked sequentially in a first direction (Z) on the conductive layer (101) and spaced apart from each other in a first region (R1a), a second region (R1b), and an extension region (R2) between the first region (R1a) and the second region (R1b), first channel structures (CHa) and second channel structures (CHb) penetrating through the stack structure (GS) and extending in the first direction (Z), respectively, in the first region (R1a) and the second region (R1b), separation regions extending in a second direction (X), the separation regions penetrating through the stack structure (GS) in the first region (R1a), the extension region (R2), and the second region (R1b), and spaced apart from each other in a third direction (Y), first insulating regions penetrating through the upper gate electrodes (130U) in each of the first and second regions (R1a, R1b) between the separation regions.