3D NAND Erase Bias Control for Uniform Threshold Voltage
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Solution Overview
Problem
Existing memory devices face issues with variations in threshold voltage distribution of memory cells after an erase operation, leading to performance degradation due to improper control of voltage input to word lines during erase operations.
Innovation Solution
The solution involves controlling the bias voltage input to word lines in memory blocks based on the characteristics of each memory block and cell, including varying the timing and level of the bias voltage to minimize threshold voltage distribution differences across different memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a uniform bias voltage is applied to all word lines during erase operation, then the erase operation can be simplified, but variations in threshold voltage distribution among different memory blocks occur
Solution Approach 1:
The patent applies different bias voltages to different groups of word lines based on their specific characteristics. Memory blocks are divided into multiple groups, and each group receives a customized bias voltage level during erase operations to compensate for variations in threshold voltage distribution, thereby achieving uniform erase characteristics across all blocks.
Solution Approach 2:
The patent changes the bias voltage parameter applied to word lines during erase operations. By adjusting the bias voltage levels dynamically and differently for different memory block groups, the patent optimizes the erase operation to minimize threshold voltage variations while maintaining manageable complexity.
2Manufacturing precision
If different bias voltages are applied to different memory blocks during erase operation, then threshold voltage distribution uniformity is improved, but the control complexity increases
Solution Approach 1:
The patent segments the memory blocks into multiple groups based on their characteristics, such as physical location or threshold voltage distribution patterns. This segmentation allows for simplified control by applying different bias voltages to different groups rather than individually to each block, reducing the overall control complexity while maintaining precision.
Solution Approach 2:
The patent implements local quality control by tailoring the bias voltage application to specific groups of word lines. Each group receives a customized bias voltage level appropriate for its characteristics, achieving uniform threshold voltage distribution across all memory blocks while managing complexity through group-based rather than individual block control.
3Reliability
If the bias voltage level is increased to ensure complete erasure, then erase completeness is improved, but threshold voltage distribution variations worsen
Solution Approach 1:
The patent applies different bias voltage levels to different groups of word lines based on their specific erase requirements. Groups that need more aggressive erasing receive higher bias voltages, while groups that are already well-erased receive lower voltages, thereby achieving complete erasure across all blocks while minimizing threshold voltage distribution variations.
Solution Approach 2:
The patent dynamically adjusts the bias voltage parameter during erase operations based on the specific characteristics of different memory block groups. By changing the voltage level appropriately for each group, the patent ensures complete erasure where needed while preventing excessive voltage application that would cause threshold voltage variations.
Data Source
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AI summary
A memory device (10) includes a cell region (20) in which memory blocks are disposed, each memory block including word lines stacked on a substrate, and channel structures penetrating through the word lines, and a peripheral circuit region (30) including peripheral circuits (31-35) executing an erase operation of deleting data for each of the memory blocks as a unit. The peripheral circuits (31-35) control a voltage applied to each word line included in a target memory block to delete data in the erase operation, based on at least one of a position of the target memory block, a height of each word line included in the target memory block, and a profile of each channel structure.